10 Specification Update
BV33 XXXNo FixClock Modulation Duty Cycle Cannot be Programmed to 6.25%
BV34 XXXNo FixProcessor May Fail to Acknowledge a TLP Request
BV35 XXXNo FixAn Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2
BV36 XXXNo Fix
A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain
Conditions
BV37 XXXNo FixPCIe* LTR Incorrectly Reported as Being Supported
BV38 XXXNo Fix
PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have
Occurred
BV39 XXXNo Fix
#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch
Instructions
BV40 XXXNo FixInterrupt From Local APIC Timer May Not Be Detectable While Being Delivered
BV41 XXXNo Fix
PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the
Specification
BV42 XXXNo Fix
PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate
with 32-bit Length Registers
BV43 XXXNo Fix
Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter
0
BV44 XXXNo FixIA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset
BV45 XXXNo Fix
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is
Followed by a REP MOVSB or STOSB
BV46 XXXNo Fix
Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial
Speed Upgrade
BV47 XXXNo FixLTR Message is Not Treated as an Unsupported Request
BV48 XXXNo Fix
64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI
Before Any Data is Transferred
BV49 XXXNo Fix
An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB May Result
EFLAGS.RF Being Incorrectly Set
BV50 XXXNo Fix
Accessing Physical Memory Space 0-640K through the Graphics Aperture May
Cause Unpredictable System Behavior
BV51 XXXNo FixPEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full
BV52 XXXNo FixInstructions Retired Event May Over Count Execution of IRET Instructions
BV53 XXXNo FixPCIe* Link May Unexpectedly Exit Loopback State
BV54 XXXNo FixThe RDRAND Instruction Will Not Execute as Expected
BV55 XXXNo Fix
A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a
System Hang
BV56 XXXNo FixPCI Express* Gen3 Receiver Return Loss May Exceed Specifications
BV57 XXXNo Fix
Direct Access Via VT-d to The Processor Graphics Device May Lead to a System
Hang
BV58 XXXNo Fix
An Event May Intervene Before a System Management Interrupt That Results from
IN or INS
BV59 XXXNo Fix
PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During
Upconfiguration
Errata (Sheet 3 of 5) Number Steppings Status ERRATA
E-1 L-1 N-0