44 Specification Update
BV81. PCIe* Link May Fail Link Width Upconfiguration
Problem: The processor supports PCIe Hardware Autonomous Width management, in which a
PCIe link can autonomously vary its width. Due to this erratum, a link that performs a
speed change while in a reduced width may no longer be able to return to a wider link
width.
Implication: PCIe links that perform speed changes while at a reduced link width may be limited to
the link width in effect at the time of the speed change. Intel has not observed this
erratum with any commercially available devices or platforms.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BV82. Graphics L3 Cache Parity Errors May Not be Detected
Problem: The graphics engine should detect parity errors within the Graphics L3 cache. However,
due to this erratum, graphics L3 cache parity errors may not be detected.
Implication: There may be undetected parity errors from workloads submitted to the execution units
of the graphics engine leading to unpredictable graphics system behavior.
Workaround: It is possible for the graphics driver to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BV83. A PCIe* Link That is in Link Disable State May Prevent DDR I/O Buffers From Entering a Power Gated State
Problem: When entering Link Disable LTSSM state, the PCIe controller may not properly indicate
the Link electrical idle condition.
Implication: An incorrect Link electrical idle indication may prevent the DDR I/O buffers from
entering a power gated state, which may cause higher power consumption on VccIO
and VccSA. Intel has not observed any functional failure or performance impact due to
this erratum.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BV84. REP MOVSB May Incorrectly Update ECX, ESI, and EDI
Problem: Under certain conditions, if the execution of a REP MOVSB instruction is interrupted,
the values of ECX, ESI and EDI may contain values that represent a later point in the
execution of the instruction than the actual interruption point.
Implication: Due to this erratum ECX, ESI, and EDI may be incorrectly advanced, resulting in
unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes