Intel BX80637I53350P

50 Specification Update

BV100. Spurious VT-d Interrupts May Occur When the PFO Bit is Set

Problem: When the PFO (Primary Fault Overflow) field (bit [0] in the VT-d FSTS [Fault Status]

erratum, further interrupts may still occur.

Implication: Unexpected Invalidation Queue Error interrupts may occur. Intel has not observed this

erratum with any commercially available software.

Workaround: Software should be written to handle spurious VT-d fault interrupts.

Status: For the steppings affected, see the Summary Tables of Changes.

BV101. Processor May Livelock During On D emand Clock Modulation

Problem: The processor may livelock when (1) a processor thread has enabled on demand clock

modulation via bit 4 of the IA32_CLOCK_MODULATION MSR (19AH) and the clock

modulation duty cycle is set to 12.5% (02H in bits 3:0 of the same MSR), and (2) the

other processor thread does not have on demand clock modulation enabled and that

thread is executing a stream of instructions with the lock prefix that either split a

cacheline or access UC memory.

Implication: Program execution may stall on both threads of the core subject to this erratum.

Workaround: This erratum will not occur if clock modulation is enabled on all threads when using on

demand clock modulation or if the duty cycle programmed in the

IA32_CLOCK_MODULATION MSR is 18.75% or higher.

Status: For the steppings affected, see the Summary Tables of Changes.

BV102. IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest Index

Value Used For VMCS Encoding

Problem: IA32_VMX_VMCS_ENUM MSR (48AH) bits 9:1 report the highest index value used for

any VMCS encoding. Due to this erratum, the value 21 is returned in bits 9:1 although

there is a VMCS field whose encoding uses the index value 23.

Implication: Software that uses the value reported in IA32_VMX_VMCS_ENUM[9:1] to read and write

all VMCS fields may omit one field.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BV103. The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging

Problem: When 32-bit paging is in use, the processor should use a page directory located at the 32-

bit physical address specified in bits 31:12 of CR3; the upper 32 bits of CR3 should be

ignored. Due to this erratum, the processor will use a page directory located at the 64-bit

physical address specified in bits 63:12 of CR3.

Implication: The processor may use an unexpected page directory or, if EPT (Extended Page Tables)

is in use, cause an unexpected EPT violation. This erratum applies only if software enters

64-bit mode, loads CR3 with a 64-bit value, and then returns to 32-bit paging without

changing CR3. Intel has not observed this erratum with any commercially available

software.

Workaround: Software that has executed in 64-bit mode should reload CR3 with a 32-bit value before

returning to 32-bit paging.

Status: For the steppings affected, see the Summary Tables of Changes.