40 Specification Update
BV67. MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate
Problem: If the processor is in a package C-state for an extended period of time (greater
than 40 seconds) with no wake events, the value in the
MSR_PKG_C{2,3,6,7}_RESIDENCY MSRs (60DH and 3F8H–3FAH) will not be accurate.
Implication: Utilities that report C-state residency times will report incorrect data in cases of long
duration package C-states.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BV68. PCIe* Link May Not Enter Loopback.Active When Directed
Problem: When an endpoint directs the processor to enter loopback slave mode at 8 GT/s via TS1
ordered sets with both the Loopback and Compliance Receive bits set, the PCIe link
should directly enter Loopback.Active state. Due to this erratum, the processor must
achieve block alignment on all looped back lanes prior to entering Loopback.Active.
Implication: The processor will not enter Loopback.Active state as a loopback slave if any lane in a
link cannot achieve block alignment.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BV69. Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM Exception
Problem: The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid-
Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-Not-
Available) exception.
Implication: Due to this erratum, some undefined instruction encodings may produce a #NM instead
of a #UD exception.
Workaround: Software should always set the vvvv field of the VEX prefix to 1111b for instances of
the VAESIM C and VAES KEYGENAS SIST inst ructions .
Status: For the steppings affected, see the Summary Tables of Changes.
BV70. Unexpected #UD on VZEROALL/VZEROUPPER
Problem: Execution of the VZEROALL or VZEROUPPER instructions in 64-bit mode with VEX.W set
to 1 may erroneously cause a #UD (invalid-opcode exception).
Implication: The affected instructions may produce unexpected invalid-opcode exceptions in 64-bit
mode.
Workaround: Compilers should encode VEX.W = 0 for the VZEROALL and VZEROUPPER instructions.
Status: For the steppings affected, see the Summary Tables of Changes.