Specification Update 33
BV41. PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the Specification
Problem: Under certain conditions, including extreme voltage and temperature, the peak-peak
voltage may be higher than the specification.
Implication: Violation of PCI Express® Base Specification of the VTX--DIFF-PP voltage. No failures
have been observed due to this erratum.
Workaround: None identified.
BV42. PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit Length Registers
Problem: In 64-bit mode, using REX.W=1 with PCMPESTRI and PCMPESTRM or VEX.W=1 with
VPCMPESTRI and VPCMPESTRM should support a 64-bit length operation with RAX/
RDX. Due to this erratum, the length registers are incorrectly interpreted as 32-bit
values.
Implication: Due to this erratum, using REX.W=1 with PCMPESTRI and PCMPESTRM as well as
VEX.W=1 with VPCMPESTRI and VPCMPESTRM do not result in promotion to 64-bit
length registers.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BV43. Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0
Problem: The processor can be configured to issue a PMI (performance monitor interrupt) upon
overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on
overflow of IA32_FIXED_CTR0, however multiple PMIs are observed when this erratum
occurs.
This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and
counter are configured as follows:
•Intel
® Hyper-Threading Technology is enabled
• IA32_FIXED_CTR0 local and global controls are enabled
• IA32_FIXED_CTR0 is set to count events only on its own thread
(IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0).
• PMIs are enabled on IA32_FIXED_CTR0 (IA32_FIXED_CTR_CTRL MSR bit [3] = ‘1)
• Freeze_on_PMI feature is enabled (IA32_DEBUGCTL MSR (1D9H) bit [12] = ‘1)
Implication: When this erratum occurs there may be multiple PMIs observed when
IA32_FIXED_CTR0 overflows.
Workaround: Disable the FREEZE_PERFMON_ON_PMI feature in IA32_DEBUGCTL MSR (1D9H)
bit [12].
Status: For the steppings affected, see the Summary Tables of Changes.