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Intel BX80637I53350P BV98. Performance Monitor Counters May Produce Incorrect Results

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Specification Update 49

BV98. Performance Monitor Counters May Produce Incorrect Results

Problem: When operating with SMT enabled, a memory at-retirement performance monitoring

event (from the list below) may be dropped or may increment an enabled event on the

corresponding counter with the same number on the physical core’s other thread rather

than the thread experiencing the event. Processors with SMT disabled in BIOS are not

affected by this erratum.

The list of affected memory at-retirement events is as follows:

MEM_UOP_RETIRED.LOADS

MEM_UOP_RETIRED.STORES

MEM_UOP_RETIRED.LOCK

MEM_UOP_RETIRED.SPLIT

MEM_UOP_RETIRED.STLB_MISS

MEM_LOAD_UOPS_RETIRED.HIT_LFB

MEM_LOAD_UOPS_RETIRED.L1_HIT

MEM_LOAD_UOPS_RETIRED.L2_HIT

MEM_LOAD_UOPS_RETIRED.LLC_HIT

MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE

MEM_LOAD_UOPS_RETIRED.LLC_MISS

MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM

MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM

MEM_LOAD_UOPS_RETIRED.L2_MISS

Implication: Due to this erratum, certain performance monitoring event may produce unreliable

results when SMT is enabled.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BV99. The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged

Problem: When a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H),

corrected errors will continue to update the lower 14 bits (bits 51:38) of the Corrected

Error Count. Due to this erratum, the sticky count overflow bit (bit 52) of the Corrected

Error Count will not get updated after a UC error is logged.

Implication: The Corrected Error Count Overflow indication will be lost if the overflow occurs after an

uncorrectable error has been logged.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

Contents

Main Page Contents Page Revision History Preface Affected Documents Related Documents Nomenclature Summary Tables of Changes Codes Used in Summary Tables Stepping Page Status Errata (Sheet 2 of 5) Errata (Sheet 3 of 5) Errata (Sheet 4 of 5) Specification Changes Specification Clarifications Errata (Sheet 5 of 5) Page Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents: Component Marking Information Table 1. Processor Identification (Sheet 1 of 6) LOT NO S/N i '10 BRAND PROC# SLxxx SPEED [COO] [FPO] Table 1. Processor Identification (Sheet 2 of 6) Table 1. Processor Identification (Sheet 3 of 6) Table 1. Processor Identification (Sheet 4 of 6) Table 1. Processor Identification (Sheet 5 of 6) Table 1. Processor Identification (Sheet 6 of 6) Errata BV1. The Processor May Report a #TS Instead of a #GP Fault BV3. IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly BV4. Performance Monitor SSE Retired Instructions May Return Incorrect Values BV5. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception BV6. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions BV7. General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted BV8. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode BV10. Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM BV11. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change BV12. B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set BV13. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error BV14. Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints BV15. LER MSRs May Be Unreliable BV16. Storage of PEBS Record Delayed Following Execution of MOV SS or STI BV17. PEBS Record not Updated when in Probe Mode BV18. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang BV19. Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word BV20. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang BV23. APIC Error Received Illegal Vector May be Lost Page BV27. Fault Not Reported When Setting Reserved Bits of Intel VT-d Queued Invalidation Descriptors BV29. VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported Field in VMCS BV30. Spurious Interrupts May be Generated From the Intel VT-d Remap Engine BV33. Clock Modulation Duty Cycle Cannot be Programmed to 6.25% BV34. Processor May Fail to Acknowledge a TLP Request BV35. An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2 BV36. A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions BV37. PCIe* LTR Incorrectly Reported as Being Supported BV38. PerfMon Overflow Status Can Not be Cleared After Certain Cond itions Have Occurred BV39. #GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions BV40. Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered BV41. PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the Specification BV42. PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit Length Registers BV43. Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0 BV44. IA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset BV46. Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial Speed Upgrade BV47. LTR Message is Not Treated as an Unsupported Request BV51. PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full BV52. Instructions Retired Event May Over Count Execution of IRET Instructions BV53. PCIe* Link May Unexpectedly Exit Loopback State BV54. The RDRAND Instruction Will Not Execute as Expected BV55. A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a System Hang BV56. PCI Express* Gen3 Receiver Return Loss May Exceed Specifications BV57. Direct Access Via VT-d to The Processor Graphics Device M ay Le ad to a System Hang BV58. An Event May Intervene Before a System Management Interrupt That Results from IN or INS BV61. Processor May Issue PCIe* EIEOS at Incorrect Rate BV62. Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe* 5GT/s Speed BV63. PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be Incorrect BV64. PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s BV66. PCIe* Link Width May Degrade After a Warm Reset BV67. MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate BV68. PCIe* Link May Not Enter Loopback.Active When Directed BV70. Unexpected #UD on VZEROALL/VZEROUPPER BV71. PCIe* Root Port May Not Initiate Link Speed Change BV72. Successive Fixed Counter Overflows May be Discarded BV73. Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM Exception BV74. VM Exits Due to NMI-Window Exiting May Not Occur Following a VM Entry to the Shutdown State BV76. PCIe* Controller May Not Properly Indicate Link Electrical Idle Condition BV77. PCIe* Controller May Not Enter Loopback BV78. Link Margin Characterization May Hang Link BV79. Unused PCIe* Lanes May Report Correctable Errors BV80. RDMSR of IA32_PERFEVTSEL{4-7} May Return Erroneous Information BV81. PCIe* Link May Fail Link Width Upconfiguration BV82. Graphics L3 Cache Parity Errors May Not be Detected BV84. REP MOVSB May Incorrectly Update ECX, ESI, and EDI BV85. Performance-Counter Overflow Indication May Cause U nd esired Behavior BV86. RDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result BV87. VEX.L is Not Ignored with VCVT*2SI Instructions Page Page BV96. IA32_MC5_CTL2 is Not Cleared by a Warm Res et BV98. Performance Monitor Counters May Produce Incorrect Results Page Page Page Specification Changes Specification Clarifications Documentation Changes BV1. On-Demand Clock Modulation Feature Clarification