Intel DG33BU specifications Parallel IDE Controller

Intel Desktop Board DG33BU Technical Product Specification

NOTE

Many Serial ATA drives use new low-voltage power connectors and require adapters or power supplies equipped with low-voltage power connectors.

For more information, see: http://www.serialata.org/

For information about	Refer to
The location of the Serial ATA connectors	Figure 10, page 42

1.7Parallel IDE Controller

The Parallel ATA IDE controller has one bus-mastering Parallel ATA IDE interface. The Parallel ATA IDE interface supports the following modes:

•Programmed I/O (PIO): processor controls data transfer.

•8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.

•Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 33 MB/sec.

•ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.

•ATA-100: DMA protocol on IDE bus allows host and target throttling. The ATA-100 logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.

•ATA-133: DMA protocol on IDE bus allows host and target throttling. The ATA-133 logic is designed to achieve read transfer rates up to 133 MB/sec and write transfer rates in excess of 100 MB/sec.

NOTE

ATA-66, ATA-100, and ATA-133 are faster timings and require a specialized cable to reduce reflections, noise, and inductive coupling.

The Parallel ATA IDE interface also supports ATAPI devices (such as CD-ROM drives) and ATA devices. The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS) translation modes. The drive reports the transfer rate and translation mode to the BIOS.

For information about	Refer to
The location of the Parallel ATA IDE connector	Figure 10, page 42

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