Intel E7501 user manual Advanced Chipset Features, DRAM Timing Control, DRAM Data Integrity Mode

BIOS SETUP

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.

Phoenix - Award WorkstationBIOS CMOS Setup Utility

Advanced Chipset Features

DRAM Timing Control	[Press Enter]	ITEM HELP
DRAM Data Integrity Mode	ECC	Menu Level
System BIOS Cacheable	Enabled
Video BIOS Cacheable	Enabled
Delayed Transaction	Enabled
Delay Prior to Thermal	16 Min

DRAM Timing Control

This field presents several options to configure the DRAM timing.

DRAM Data Integrity Mode

This BIOS feature controls the ECC feature of the memory controller. ECC, which stands for Error Checking and Correction, enables the memory controller to detect and correct single-bit soft memory errors. The memory controller will also be able to detect double-bit errors although it will not be able to correct them. This provides increased data integrity and system stability. However, this feature can only be enabled if you are using special ECC memory modules.

System BIOS Cacheable

The setting of Enabled allows caching of the system BIOS ROM at F000h-FFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result.

Video BIOS Cacheable

The Setting Enabled allows caching of the video BIOS ROM at C0000h-F7FFFh, resulting in better video performance. However, if any program writes to this memory area, a system error may result.

Delayed Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2.1.

Delay Prior to Thermal

This field activates the CPU thermal function after the systems boots for the set number of minutes. The options are 16Min and 64Min.

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