BIOS SETUP
40 IB865 User’s Manual
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable By SPD ITEM HELP
CAS Latency Time 2.5 Menu Level
Active to Precharge Delay 6
DRAM RAS# to CAS# Delay 3
DRAM RAS# Precharge 3
Memory Frequency For Auto
System BIOS Cacheable Enabled
Video BIOS Cacheable Disabled
Memory Hole at 15M-16M Disabled
Delay Prior to Thermal 16 Min
AGP Aperture Size (MB) 128
Init Display First Onboard/AGP
** On-Chip VGA Setting **
On-Chip VGA Enabled
On-Chip Frame Buffer Size 8MB
Boot Display CRT + LVDS
Panel Scaling Auto
Panel Number 1024x768 LVDS
TV Standard Off
Video Connector Automatic
TV Format Auto
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected.
The default is By SPD.
CAS Latency Time
You can select CAS latency time in HCLKs of 2/2 or 3/3. The system
board designer should set the values in this field, depending on the
DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU. The
choices are 2 and 3.
Active to Precharge Delay
The default setting for the Active to Precharge Delay is 6.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address
Strobe) and CAS (Column Address Strobe) signals. This delay occurs
when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.