Jtag Boundary Scan Port, Framer/ASIC Connection | Intel LXD386

LXD386 — Evaluation Board for Quad T1/E1 Applications

Figure 3. Jumper Block JP5

3.11JTAG Boundary Scan Port

The eight pin connector JP2 shown in Figure 4 provides access to the IEEE 1149.1 compliant JTAG boundary scan port for board testing purposes.

Figure 4. Jumper Block JP2

3.12Framer/ASIC Connection

Ten pin connectors provide access to the digital signals necessary for interfacing with the back-end Framer/Mapper or ASIC. Figure 5 represents one of the four connectors with the factory jumper connecting RCLK to TCLK.

12	Developer Manual

Image 12

Intel LXD386 manual Jtag Boundary Scan Port, Framer/ASIC Connection

Contents

LXD386 Evaluation Board for Quad T1/E1 Applications Developer ManualPage Contents Figures Tables Features General Description LXD386 Evaluation Board for Quad T1/E1 Applications Overview LXD386 Packing ListEquipment Requirements Control Modes Factory Settings Hardware Mode Set-Up and Operation Power ConnectionsHardware Mode Selection Loopback Mode Selection Output Enable Selection Code SelectionMonitoring Address Selection Jitter Attenuator Selection Master Clock Setup Line Buildout Selection Jtag Boundary Scan Port Framer/ASIC Connection LED Indicators Line InterfaceBoard Protection Software Mode Set-Up and Operation I8051 Microcontroller BoardEvaluation Board Set-up Test Equipment Connections Software Installation and Start-Up Evaluation Board SoftwareHardware Set-up Screen Quitting the Program Configuration Screen Communications Modes Apply to all Channels Setting Registers Registers Screen Registers Screen LXD386 Interface Unit Evaluation Board Applications Firebird LXD386 For