Intel PCM-6896 manual SDRAM CAS Latency Time, SDRAM Cycle Time Tras/Trc, SDRAM RAS-to-CAS Delay

Advanced Chipset Features

SDRAM CAS Latency Time

When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from

the default value specified by the system designer.

SDRAM Cycle Time Tras/Trc

Select the number of SCLKs for an access cycle.

The choices: 5/7, 6/8, 7/9.

SDRAM RAS-to-CAS Delay

This field lets you insert a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from, or refreshed. Fast gives faster performance; slow gives more stable performance. This field applies only when synchronous DRAM is installed in the system.