Intel S3420GP POST Error Beep Codes

IntelP®P Server Board S3420GP TPS Appendix D: POST Code Errors

Error Code Error Message Response

0xA500 ATA/ATPI ATA bus SMART not supported. No Pause

0xA501 ATA/ATPI ATA SMART is disabled. No Pause

0xA5A0 PCI Express* component encountered a PERR error. No Pause

0xA5A1 PCI Express* component encountered a SERR error. Halt

0xA5A4 PCI Express* IBIST error. Pause

0xA6A0 DXE boot services driver Not enough memory available to shadow a legacy option ROM. No Pause

POST Error Beep Codes

The following table lists POST error beep codes. Prior to system video initialization, the BIOS

uses these beep codes to inform users on error conditions. The beep code is followed by a

user-visible code on POST Progress LEDs.

Table 70. POST Error Beep Codes

Beeps Error Message POST Progress Code Description

3 Memory error Multiple System halted because a fatal error related to the memory

was detected.

Revision 1.0

Intel order number E65697-003

117

Contents

Main Intel Server Board S3420 GP Technical Product Specification Revision History Disclaimers Table of Contents Page Page Page List of Figures Page List of Tables Page Page Page 1. Introduction 1.1 Chapter Outline 1.2 Server Board Use Disclaimer IntelPP Server Board S3420GP TPS Overview 2. Overview 1 2.1 Intel Server Board S3420GP Feature Set Table 1. Intel Server Board S3420GP Feature Set Revision 1.0 Intel order number E65697-003 Overview IntelPP Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 2 Page Overview IntelPP Server Board S3420GP TPS 2.2.1 Server Board Connector and Component Layout 4 DD CC AF003290 IntelPP Server Board S3420GP TPS Overview Table 2. Major Board Components Revision 1.0 Intel order number E65697-003 5 2.2.2 Intel Server Board S3420GP Mechanical Drawings Page Page Page Page Page 2.2.3 Server Board Rear I/O Layout IntelPP Server Board S3420GP TPS Functional Architecture 3 nct. Fu ional Architecture 13 FLASH Slot 4 3.1 The t Xeon The Intel Xrocessors processors are made up of multi-core processors based 3.1.1 3.2 Memory Subsystem 3 Simultaneous Multithreading tel SpeedStep Technology 3.2.1 Memory Sizing and Configuration 3.2.2 Post Error Codes 3.2. 3 Publishing System Memory xed-speed Memory Modules 3.2.4 Support for Mi 3.2.5 Memory Map and Population Rules Page Page 3.3 Intel 3420 Chipset PCH 3.4 I/O Sub -system 3.4.1 PCI Express Interface 3.4.2 Serial ATA Support 3.4.3 USB 2.0 Support 3.5 Optional SAS Entry RAI Intel D Module AXX4SASMOD 3.6 Integrated Baseboard Management Controller Page IntelPP Server Board S3420GP TPS Functional Architecture BMC & KVMS Subsystem 25 BMC & KVMS Subsystem Graphics Subsystem 3.6.1 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10/100 network interfaces. Interface 1: Integrated BMC Block Diagram All users disabled 3.6.2 Optional RMM3 Advanced Management Board 3.6.3 Serial Ports 3.6.4 3.6.5 Floppy Disk Controller Keyboard and Mouse Support 3.7 3.7 Wake-up Control Video Support .1 Video Modes 3.8 ller (NIC) 3.8 efinition Network Interface Contro 3.8.1 GigE Controller 82574L 3.1 3.9 Intel I/O Acceleration Technolgy 2 (Intel I/OAT2) Direct Cache Access (DCA) 0 Intel Virtualization Technology for Directed I/O (Intel VT-d) 4. Platform Management 4.1 Feature Support 4.1.1 IPMI 2.0 Features 4.1.2 Non-IPMI Features ptional Adv 4.2 O anced Management Feature Support 4.2.1 Enabling Advanced Management Features 4.2.2 Keyboard, Video, Mouse (KVM) Redirection 4.2.3 Media Redirection 4.2.4 Web Services for Management (WS-MAN) hentication Protocol (LDAP) d Webserver 4.3 M 4.2.5 Local Directory Aut 4.2.6 Embedde anagement Engine (ME) 5. BIOS User Interface 5.1 n 5.2 BIOS Boot Popup Menu 5.3 BIOS Setup utility 5.3.1 Operation Page IntelPP Server Board S3420GP TPS BIOS User Interface Table 10. BIOS Setup: Keyboard Command Bar Revision 1.0 Intel order number E65697-003 37 5.3.2 tform Setup tility Screens Server Pla U Page Page Page Page Page emory Screen screen f the M een, select Advanced > Memor Page T To access this screen from the Main menu, select Advanced > Mass Storage. Page 2.5 uratio The USB Conf reen a ntroller op To access this guration. Page .3.2.2.6 PCI Screen tions. 5.3.2.2.7 Sy Th 51 Revision 1.0 Intel order number E65697-003 Page Page anagement screen allows the user to configure several server manage Server Manage Page BIOS User Interface IntelPP Server Board S3420GP TPS 56 Console Redirection Server Management 57 Revision 1.0 Intel order number E65697-003 T n e media encou te s user to configure t . Page Page Page Page boo vice for im g t ystem. ss t scree n, s ct Boot Manager. 5.4 Loading BIOS Defaults Different mechanisms exist for resetting th Page IntelPP Server Board S3420GP TPS Connector/Header Locations and Pin-outs 6. Connector / Header Locations and Pin-outs 65 . Board Connector Matrix 6.1 The fol jumper corresp 6.3 System Management Headers 6.3.1 Intel Remote Management Module 3 (Intel RMM3) Connector 6.3.2 L / IP CP MB Header 6.3.3 HSB P Header 6.3.4 SGP 6.4 Front Control Panel Connector 6.4.1 Power Button 6.4.2 Reset B ton 6.4.3 NMI Butto 6.4.4 System S tus LE ut n ta Indicator D Connector/Header Locations and Pin-outs IntelPP Server Board S3420GP TPS 70 Table 39. System Status LED Indicator States Revision 1.0 Intel order number E65697-003 IntelPP Server Board S3420GP TPS Connector/Header Locations and Pin-outs 6.5 I/O Connectors 71 Table 41. RJ- 100/1000 NI nne -out ( 6.5.1 VGA Connector The following table details the pin-out definition of the VGA connector (J7A1). 6.5.3 SATA 72 Table 43. SATA Connector Pin-out (J1H4, J1H1, J1G1, J1H3, J1G3, J1F4) 6.5.4 SAS Connectors Table 44. SAS Connector Pin-out (J2H1) 6.5.6 USB Connector One x connector (J1J2) on the server board provides an option to support a USB floppy connector. IntelPP Server Board S3420GP TPS Connector/Header Locations and Pin-outs 6.6 PCI Express* Slot / PCI Slot / Riser Card Slot / 75 Table 50. Pin-out of adaptive riser slot / PCI Express slot 6 Revision 1.0 Intel order number E65697-003 Page Three PCI Express* x8 connectors (J2B2, J3B1 and J4B2) One PCI Express* X4 connector (J2B1) One PCI X32 connector (J1B1) 6.7 Fan Headers 7. Jumper Blocks 7.1 CMOS Clear and Password Reset Usage Procedure 7.1.1 Clearing the CMOS 7.1.2 Clearing the Password 7.2 Integrated BMC Force Update Procedure 7.3 ME Force Update Jumper 7.4 BIOS Recovery Jumper Intel Light Guided Diagnostics IntelPP Server Board S3420GP TPS 8. Intel Light Guided Diagnostics 84 8.1 System Status LED Table 53. Front Panel Status LED Behavior Summary Revision 1.0 Intel order number E65697-003 8.2 Post Code Diagnostic LEDs 9. Design and Environmental Specifications 9.1 Intel Server Board S3420GP Design Specifications 9.2 Board-level Calculated MTBF 9.3 Server Board Power Requirements 9.3.1 Processor Power Support 9.4 Power Supply Output Requirements 9.4.1 Grounding 9.4.2 Standby Outputs 9.4.3 Remote Sense 9.4.4 Voltage Regulation 9.4.5 Dynamic Loading 9.4.6 Capacitive Loading 9.4.7 Closed-loop Stability 9.4.8 Common Mode Noise 9.4.9 Ripple / Noise 9.4.10 Timing Requirements Page Figure 38. Turn On/Off Timing (Power Supply Signals) Revision 1.0 Intel order number E65697-003 92 9.4.11 Residual Voltage Immunity in Standby Mode 9.4.12 Protection Circuits Page 10. Regulatory and Certification Information 10.1 Product Regulatory Compliance 10.1.1 Product Safety Compliance 10.1.2 Product EMC Compliance Class A Compliance 10.1.3 Certifications / Registrations / Declarations 10.1.4 Product Ecology Requirements IntelPP Server Board S3420GP TPS Regulatory and Certification Information Revision 1.0 Intel order number E65697-003 97 10.2 Product Regulatory Compliance Markings The server board is provided with the following regulatory marks. Regulatory and Certification Information IntelPP Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 98 10.3 10.3.1 Electromagnetic Compatibility Notices FCC Verification Statement (USA) Page Page Appendix A: Integration and Usage Tips Appendix B: Integrated BMC Sensor Tables Page IntelPP Server Board S3420GP TPS Appendix B: Integrated BMC Sensor Tables Revision 1.0 Intel order number E65697-003 105 Table 66. Integrated BMC Core Sensors Appendix B: Integrated BMC Sensor Tables 106 Revision 1.0 Intel order number E65697-003 IntelPP Server Board S3420GP TPS Appendix B: Integrated BMC Sensor Tables Revision 1.0 Intel order number E65697-003 107 Appendix B: Integrated BMC Sensor Tables 108 Revision 1.0 Intel order number E65697-003 Appendix C: POST Code Diagnostic LED Decoder Revision 1.0 Intel order number E65697-003 110 IntelPP Server Board S3420GP TPS Appendix C: POST Code Diagnostic LED Decoder Revision 1.0 Intel order number E65697-003 111 112 0XF9h O X X O X X X X Resetting the keyboard 0xFAh O X X O X X X O Revision 1.0 Intel order number E65697-003 Appendix D: POST Code Errors Revision 1.0 Intel order number E65697-003 114 IntelPP Server Board S3420GP TPS Appendix D: POST Code Errors Revision 1.0 Intel order number E65697-003 115 Revision 1.0 Intel order number E65697-003 116 POST Error Beep Codes Appendix E: Supported Intel IntelPP Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 119 Glossary Glossary IntelPP Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 120 IntelPP Server Board S3420GP TPS Revision 1.0 Intel order number E65697-003 121 Reference Documents