ATM2 OC12/STM4 IQ PIC
■JUNOS 5.5 and laterSoftware release
■One OC12 port
■Power requirements: 0.41 A/48 V @ 20 W
■Intelligent queuing (IQ) PICs support fine-grained queuing per logical interface
■Conforms to ANSI T1.105-1991 and T1E1.2/93-020R1
■Complies with ATM and SONET/SDH standards
■Alarm and event counting and detection
■Compatible with well-known ATM switches
■ATM switch ID, which displays the switch IP address and local interface name of the
adjacent Fore ATM switches
Description
■One 3010 SAR for segmentation and reassembly into 53 byte ATM cells
■High-performance parsing of SONET/SDH frames
■ASIC-based packet segmentation and reassembly (SAR) management and output port
queuing
■64 MB SDRAM memory for ATM SAR
■Packet buffering, Layer 2 parsing
Hardware features
■Circuit cross-connect for leveraging ATM access networks
■User-configurable virtual circuit (VC) and virtual path (VP) support
■Support for idle cell or unassigned cell transmission
■OAM fault management processes alarm indication signal (AIS), remote defect indication
(RDI), and loop cells
■Point-to-point and point-to-multipoint mode Layer 2 counters per VC and per VP
■Local and remote loopback
■ATM Inverse ARP, which enables routers to automatically learn the IP address of the
router on the far end of an ATM PVC
■Simple Network Management Protocol (SNMP):
■Management Information Base (MIB) 2 (RFC 1213)
■ATM MIB (RFC 1695)
■SONET MIB
■Unspecified bit rate (UBR), non-real-time variable bit rate (VBR), and constant bit rate
(CBR) traffic shaping
■Per-VC or per-VP traffic shaping
■Support for F4 OAM cells
■Support for 16-bit VCI range
Software features
20 ■ATM2 OC12/STM4 IQ PIC
M20 Internet Router PIC Guide