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| UPD63711AGC(2/3) | |
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Pin No. | Symbol | I/O | Function |
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33 | IO11 | I | LRCK signal input terminal to building DAC into. |
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34 | IO12 | O | Signal which distinguishes left channel/right channel of voice data output |
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| from DOUT. |
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35 | IO13 | O | Terminal (88.2kHz)(WDCK)of the output of the frequency signal twice |
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| defect detection output terminal(HOLD) LRCK HOLD/WDCK can be |
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| switched with the microcomputer. |
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36 | VSSO | O | Terminal of output of data of Digital audio interface. |
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37 | VDD1 | - | It is GND of the logic circuit. |
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38 | IO14 | O | Buffer ring output terminal of oscillation. |
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39 | IO15 | I | The state of this terminal is output to Bit5 of the status output. |
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40 | DREQ | - | Positive power supply supply terminal to logic circuit. |
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41 | DRESP | O | It is |
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42 | IOP7 | O | output of the synchronous pattern detection signal and the frame |
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| counter is corresponding by the EFM recovery part, and becomes a row |
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| level at the disagreement. |
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43 | IOP6 | O | Mirror output terminal. (MIRR).It is a frame synchronous signal of PLL |
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| system. The one that a basic frequency (44.1kHz)of the reading signal |
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| obtained in PLL system was divided makes almost equally to the |
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| synchronization(7.35kHz) of one frame. (WFCK)MIRR/WFCK can be |
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| switched with the microcomputer. |
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44 | IOP5 | O | the terminal for the monitor of the bit clock. When PLL is locked, the |
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| go down edge of the EFM signal and this signal locks. |
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45 | IOP4 | - | it is GND of the logic circuit. |
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46 | IOP3 | O | The output terminal which shows the C1 error correction result. Even |
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47 | IOP2 |
| go down of RFCK is fixed. |
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48 | IOP1 | O | It is an output terminal which shows the C2 error correction result. Even |
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49 | IOP0 |
| of RFCK is fixed. |
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50 | HDBDIR |
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51 | DVDD | - | Positive power supply supply terminal to logic circuit. |
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52 | PACK | O | It is PACK synchronous signal shows the head of packing. |
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53 | TSO | O | It is a cereal output terminal of the |
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54 | TSI | I | It is a serial input terminal of the |
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55 | TSCK_B | I | Cereal clock input terminal of |
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56 | TSTB_B | I | Terminal of input of parameter strove signal of |
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57 | DGND | - | It is GND of the logic circuit. |
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58 | TEST0 | I | It is a test terminal. Please connect with GND usually. |
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59 | TEST1 |
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60 | ATEST | O | It is a test terminal. Please make to the opening usually. |
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61 | AGND | - | It is GND of an analog circuit. |
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62 | FD | O | Focus drive output terminal. |
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63 | TD | O | Tracking drive output terminal. |
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64 | SD | O | Thread drive output terminal. |
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65 | MD | O | Spindle drive output terminal. |
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66 | DACO | O | It is DAC output terminal for the adjustment. A set value of CRAM7FH is |
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| output. |
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67 | FBAL | O | It is DAC output terminal for the adjustment. A set value of CRAM7CH is |
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| output |
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68 | TBAL | O | It is DAC output terminal for the adjustment. A set value of CRAM7DH is |
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| output. |
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69 | TEVCA | O | It is DAC output terminal for the adjustment. A set value of CRAM7EH is |
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| output |
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70 | AVDD | - | It is a positive power supply supply terminal to an analog circuit. |
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71 | EFM | O | EFM signal output terminal. |
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72 | ASY | I | It is a standard voltage input terminal of the EFM comparator. |
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73 | C3T | - | Capacitor connection terminal for 3T detection. |
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74 | RFI | I | RF signal input terminal for EFM data generation. |
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75 | AGCO | O | RF signal output terminal after gain is adjusted. |
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76 | AGCI | I | Input terminal of |
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77 | RFO | O | Output terminal of RF saming amplifier. |
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