Marantz SA-17S1 Phrefi, Phrefo, Zdfr, Dsar, Vddsd, Zdfc, Dsac, Zdflfe, Dsalfe, Zdfls, Wck

61	PHREFI	I	Phase reference signal input for DSD output phase modulation.
62	PHREFO	O	Phase reference signal output for DSD output phase modulation.
63	ZDFL	O	Lch zero data detection flag (when set by the microcomputer). Goes high when silent data continues for 300ms.
64	DSAL	O	Lch DSD data output.
65	ZDFR	O	Rch zero data detection flag (when set by the microcomputer). Goes high when silent data continues for 300ms.
66	DSAR	O	Rch DSD data output.
67	VDDSD	—	Power supply for DSD data output. Supply +3.3V separated from other digital power supplies.
68	ZDFC	O	Cch zero data detection flag (when set by the microcomputer). Goes high when silent data continues for 300ms.
69	DSAC	O	Cch DSD data output.
70	ZDFLFE	O	LFEch zero data detection flag (when set by the microcomputer). Goes high when silent data continues for
			300ms.
71	DSALFE	O	LFEch DSD data output.
72	VSDSD	—	GND for DSD data output.
73	ZDFLS	O	LSch zero data detection flag (when set by the microcomputer). Goes high when silent data continues for
			300ms.
74	DSALS	O	LSch DSD data output.
75	ZDFRS	O	RSch zero data detection flag (when set by the microcomputer). Goes high when silent data continues for
			300ms.
76	DSARS	O	RSch DSD data output.
77	VDDSD	—	Power supply for DSD data output. Supply +3.3V separated from other digital power supplies.
78	TESTO	O	Test output. Leave open.
79	TESTO	O	Test output. Leave open.
80	VSC	—	Core GND.
81	TESTO	O	Test output. Leave open.
82	TESTO	O	Test output. Leave open.
83	VDC	—	Core power supply. Supply +2.5V.
84	TESTO	O	Test output. Leave open.
85	TESTO	O	Test output. Leave open.
86	VSIO	—	I/O GND.
87	TESTO	O	Test output. Leave open.
88	TESTI	I	Test input. Fix to low.
89	TESTI	I	Test input. Fix to low.
90	VDIO	—	I/O power supply. Supply +3.3V.
91	TESTO	O	Test output. Leave open.
92	TESTO	O	Test output. Leave open.
93	TESTO	O	Test output. Leave open.
94	VSC	—	Core GND.
95	TESTI	I	Test input. Fix to high.
96	TESTI	I	Test input. Fix to low.
97	TESTI	Ipu	Test input. Fix to high.
98	TESTO	O	Test output. Leave open.
99	VDC	—	Core power supply. Supply +2.5V.
100	TESTI	I	Test input. Fix to low.
101	TESTI	I	Test input. Fix to low.
102	TESTI	I	Test input. Fix to low.
103	TESTI	I	Test input. Fix to low.
104	TESTI	I	Test input. Fix to low.
105	TESTI	I	Test input. Fix to low.
106	VSIO	—	I/O GND.
107	TESTI	I	Test input. Fix to low.
108	TESTI	I	Test input. Fix to low.
109	TESTI	I	Test input. Fix to low.
110	VDIO	—	/O power supply. Supply +3.3V.
111	WAD0	I	External A/D data input for PSP physical disc mark detection. (LSB) This is used only when not using the
			internal A/D converter and connecting an external A/D converter.
112	WAD1	I	External A/D data input for PSP physical disc mark detection.
113	WAD2	I	External A/D data input for PSP physical disc mark detection.
114	WAD3	I	External A/D data input for PSP physical disc mark detection.
115	VSIO	—	I/O GND.
116	VSC	—	Core GND.
117	WAD4	I	External A/D data input for PSP physical disc mark detection.
118	WAD5	I	External A/D data input for PSP physical disc mark detection.
119	WAD6	I	External A/D data input for PSP physical disc mark detection.
120	WAD7	I	External A/D data input for PSP physical disc mark detection. (MSB)
121	VDC	—	Core power supply. Supply +2.5V.
122	TESTI	I	Test input. Fix to low.
123	WCK	I	Operating clock for PSP physical disc mark detection. Input the PLL clock corresponding to 1T of RF.
124	WAVDD	—	A/D power supply for PSP physical disc mark detection. Input +2.5V separated from the digital block.
125	WAVDD	—	A/D power supply for PSP physical disc mark detection. Input +2.5V separatedfrom the digital block.

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