Maxim manual MAX9777/MAX9778, Digital Interface, SMBus is a trademark of Intel Corp

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MAX9777/MAX9778

Digital Interface

The MAX9777 features an I2C/SMBus™-compatible 2- wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facili- tate bidirectional communication between the MAX9777 and the master at clock rates up to 400kHz. Figure 3 shows the 2-wire interface timing diagram. The MAX9777 is a transmit/receive slave-only device, rely- ing upon a master to generate a clock signal. The mas- ter (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer.

A master device communicates to the MAX9777 by transmitting the proper address followed by a com- mand and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) con- dition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.

SDA and SCL are open-drain outputs requiring a pullup resistor (500Ω or greater) to generate a logic-high volt- age. Series resistors in line with SDA and SCL are option- al. These series resistors protect the input stages of the

SMBus is a trademark of Intel Corp.

devices from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.

Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy.

START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issu- ing a START condition. A START condition is a high-to- low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of a transmission to the MAX9777. The master terminates transmission by issuing the STOP condition; this frees the bus. If a REPEATED START condition is generated instead of a STOP condition, the bus remains active.

SDA
tSU, DAT	tHD, STA		tBUF
		tSP
	tHD, STA
tLOW	tHD, DAT	tSU, STO
SCL
tHIGH
tHD, STA
tR	tF
START	REPEATED	STOP	START
CONDITION	START	CONDITION	CONDITION
	CONDITION

Figure 3. 2-Wire Serial-Interface Timing Diagram

S Sr P

SCL

SDA

Figure 4. START/STOP Conditions

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