Maxtor 2R010H1, 2R015H1 DMA TimingDMA Timing, DMA TimingDMA Timing DMA Timing

AT INTERFACE DESCRIPTION
5 – 4
DMA TimingDMA Timing
DMA TimingDMA Timing
DMA Timing
TIMING PARAMETE RS MODE 0 MODE 1 MODE 2
t0 Cycle Time (min) 480 ns 150 ns 120 ns
tC DMACK to DMARQ delay
tD DIOR-/DIOW- (min) 215 ns 80 ns 70 ns
tE DIOR- data access (min) 150 ns 60 ns
tF DIOR- data hold (min ) 5 ns 5 ns 5 ns
tG DIOR-/DIOW- data setup (min) 100 ns 30 ns 20 ns
tH DIO W- d ata hold (min ) 20 ns 1 5 ns 1 0 ns
tI DMACK to DIOR-/DIOW- setup (min) 0 0 0
tJ DIOR-/DI OW- to D M A CK ho ld (min) 2 0 ns 5 ns 5 ns
tKr DIOR- nega ted puls e wi dt h (min ) 50 ns 50 ns 2 5 ns
tKw DIOW- negated pulse width (min) 215 ns 50 ns 25 ns
tLr DIOR- to D MA RQ de la y (max ) 120 ns 40 ns 35 ns
tLw DIOW- to DMARQ dela y (ma x) 40 ns 4 0 ns 35 ns
tZ DMACK - to tr ist a te (max) 20 ns 25 ns 25 ns
Figure 5 - 3
Multi-word DMA Data Transfer