AT INTERFACE DESCRIPTION
Pin Description Table
PIN NAME | PIN | I/O | SIGNAL NAME | SIGNAL DESC RIPTION |
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RESET - | 01 | I | Hos t Reset | Reset signal from the host s ystem. Active during power up and inactive after. |
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D D0 | 17 | I/O | Host Data Bus | 16 bit |
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| register and EC C byte transfers. All 16 bits us ed for data transfers. |
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D D1 | 15 | I/O |
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D D2 | 13 | I/O |
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D D3 | 11 | I/O |
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D D4 | 09 | I/O |
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D D5 | 07 | I/O |
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D D6 | 05 | I/O |
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D D7 | 03 | I/O |
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D D8 | 04 | I/O |
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D D9 | 06 | I/O |
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DD 10 | 08 | I/O |
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D D11 | 10 | I/O |
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DD 12 | 12 | I/O |
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DD 13 | 14 | I/O |
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DD 14 | 16 | I/O |
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DD 15 | 18 | I/O |
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D MARQ | 21 | O | DM A Request | This signal is used with DM AC K for D MA transfers . By asserting this s ignal, the |
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| drive indicates that data is ready to be transfered to and from the host. |
DIOW - | 23 | I | Host I/O Write | Rising edge of Write strobe clock s data from the hos t data bus to a register on |
STOP |
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| the drive. |
D IOR - | 25 | I | Host I/O Read | Read strobe enables data from a register on the drive onto the host data bus. |
HD MARDY |
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| DMA ready during UltraDMA data in bursts. |
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| Data strobe during UltraDMA data out bursts. |
HSTROBE |
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IORDY | 27 | O | I/O C hannel Ready | This signal may be driven low by the drive to insert wait states into host I/O |
DD MARDY |
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| cycles. |
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| D MA ready during UltraDMA data out bursts. |
DSTROBE |
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| D ata strobe during UltraDMA data in bursts. |
CSEL | 28 |
| C able Select | Us ed for Mas ter/Slave selection via cable. Requires s pecial cabling on host |
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| s ystem and installation of C able Select jumper. |
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D MACK - | 29 | I | D MA Acknowledge | This signal is used with DM ARQ for D MA transfers . By asserting this s ignal, the |
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| host is ac knowledging the receipt of data or is indicating that data is available. |
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INTRQ | 31 | O | Hos t Interrupt | Interrupt to the host asserted when the drive requires attention from the host. |
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| Request |
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IOC S16 | 32 |
| D evice 16 bit I/O | Obsolete |
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PD IAG - | 34 | I/O | Pas sed D iagnostic | Output by drive when in Slave mode; Input to drive when in Master mode. |
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DA0 | 35 | I | Hos t Address Bus | 3 bit binary address from the host to selec t a regis ter in the drive. |
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DA1 | 33 | I |
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DA2 | 36 | I |
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C S0 - | 37 | I | Host Chip Select 0 | C hip selec t from the host used to access the C omm and Block registers in the |
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| drive. This signal is a decode of I/O addres ses 1F0 - 1F 7 hex. |
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C S1 - | 38 | I | Host Chip Select 1 | Chip select from the host used to access the Control registers in the drive. This |
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| signal is a decode of I/O addres ses 3F6 - 3F 7 hex. |
DASP - | 39 | I/O | Drive Active/D rive | |
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| 1 Present | that |
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| device 1 is pres ent. |
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GND | 02 | N/A | Ground | Signal ground. |
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| 24 |
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| 26 |
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| 40 |
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KEY | 20 | N/A | Key | Pin used for keying the interface connector. |
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