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Counters
Table 9. Counter specifications
Parameter |
| Specification |
| |
|
|
|
|
|
Counter type |
| 82C54 |
| |
Configuration | Two 82C54 devices. 3 down counters per 82C54, 16 bits each | |||
82C54A: |
| Counter 0 - ADC residual | Source: | ADC Clock |
|
| sample counter | Gate: | Internal programmable source |
|
|
| Output: | |
|
| Counter 1 - ADC pacer lower | Source: | 10 MHz oscillator |
|
| divider | Gate: | Tied to counter 2 gate, programmable source |
|
|
| Output: | Chained to counter 2 clock |
|
| Counter 2 - ADC pacer upper | Source: | Counter 1 output |
|
| divider | Gate: | Tied to counter 1 gate, programmable source |
|
|
| Output: | ADC pacer clock (if software selected). Available at |
|
|
|
| user connector. |
82C54B: |
| Counter 0 - pretrigger mode | Source: | ADC clock |
|
|
| Gate: | External trigger |
|
|
| Output: | |
|
| Counter 0 - user counter 4 | Source: | User input at |
|
| (when in |
| or internal 10 MHz (software selectable) |
|
|
| Gate: | User input at |
|
|
| Output: | Available at |
|
| Counter 1 - user counter 5 | Source: | User input at |
|
|
| Gate: | User input at |
|
|
| Output: | Available at |
|
| Counter 2 - user counter 6 | Source: | User input at |
|
|
| Gate: | User input at |
|
|
| Output: | Available at |
Clock input frequency | 10 MHz max |
| ||
High pulse width (clock input) | 30 ns min |
| ||
Low pulse width (clock input) | 50 ns min |
| ||
Gate width high | 50 ns min |
| ||
Gate width low | 50 ns min |
| ||
Input low voltage | 0.8 V max |
| ||
Input high voltage | 2.0 V min |
| ||
Output low voltage | 0.4 V max |
| ||
Output high voltage | 3.0 V min |
| ||
Crystal oscillator frequency | 10 MHz |
| ||
Frequency accuracy | 50 ppm |
|
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