MS-7750

▶tRCD

When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance.

▶tRP

This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system.

▶tRAS

This setting determines the time RAS takes to read from and write to memory cell. ▶tRFC

This setting determines the time RFC takes to read from and write to a memory cell.

▶tWR

Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells.

▶tWTR

Minimum time interval between the end of write data burst and the start of a column -read command. It allows I/O gating to overdrive sense amplifiers before read command starts.

▶tRRD

Specifies the active-to-active delay of different banks. ▶tRTP

Time interval between a read and a precharge command. ▶tFAW

This item is used to set the tFAW (four activate window delay) timing.

▶tWCL

This item is used to set the tWCL (Write CAS Latency) timing.

▶tCKE

This item is used to set the tCKE timing. ▶tRTL

This item is used to set the tRTL timing.

▶Advanced Channel 1/ 2 Timing Configuration

Press <Enter> to enter the sub-menu. And you can set the advanced memory timing for each channel.

3 Chapter

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