National Instruments DAQCard-1200 The GATE and OUT signals in Figure3-19 are referenced to the rising edge of the CLK signal.

Chapter 3 Signal Connections
DAQCard-1200 User Manual 3-30 © National Instruments Corporation
Figure3-19 shows the timing requirements for the GATE and CLK input
signals and the timing specifications for the OUT output signals of
the 82C53.
Figure 3-19. General-Purpose Timing Signals
The GATE and OUT signals in Figure3-19 are referenced to the rising edge
of the CLK signal.
tsc tpwh tpwl
tgsu tgh
tgwh tgwl
toutc
toutg
CLK
GATE
OUT
VOH
VIH
VIL
VIH
VOL
VIL
tsc
tpwh
tpwl
tgsu
tgh
tgwh
tgwl
toutg
toutc
clock period
clock high level
clock low level
gate setup time
gate hold time
gate high level
gate low level
output delay from clock
output delay from gate
380 ns min
230 ns min
150 ns min
100 ns min
50 ns min
150 ns min
100 ns min
300 ns max
400 ns max