Chapter 3 Signal Connections
DAQCard-1200 User Manual 3-26 © National Instruments Corporation
this case is triggered by a low level on the EXTUPDATE* line. The
counter-interrupt signal interrupts the PC. This interrupt is generated on the
rising edge of EXTUPDATE*. The DACWRT signal writes a new value to
the DAC.
Figure 3-16. EXTUPDATE* Signal Timing for Updating DAC Output
The following rating applies to the EXTCONV*, EXTTRIG, OUTB1, and
EXTUPDATE* signals.
• Absolute maximum voltage input rating –0.5 to 5.5 V with respect
to DGND
For more information concerning the various modes of data acquisition and
analog output, refer to your NI-DAQ manual or to Chapter4, Theory of
Operation.
Note You should configure both DACs in either immediate update mode or in later
update mode, but not in a combination of the two modes. Although you can
configure the DACs in a combination of modes, doing so can result in glitches on
the immediate update DAC if the update rate on the waveform DAC is high. Please
refer to the Analog Output section in Chapter 4, Theory of Operation, for details
on this behavior.
General-Purpose Timing Signal Connections
General-purpose timing signals include the GATE, CLK, and OUT signals
for the three 82C53(B) counters. The 82C53 counter/timers can be used for
general-purpose applications such as pulse and square wave generation;
event counting; and pulsewidth, time-lapse, and frequency measurement.
For these applications, the CLK and GATE signals at the front
I/O connector control the counters. The single exception is counter B0,
EXTUPDATE*
DAC OUTPUT
UPDATE
DACWRT
tw50 ns min
Counter Interrupt