Chapter2 HardwareOverview
©NationalInstruments Corporation 2-5 NI5620 User Manual
Block Diagram
Thisblock diagram is intended for advanced users. An explanation of some
ofthese f eatures follows.
Figure2-3. BlockDiagram
The digital downconverter is a digital signal processor (DSP) that allows
you to digitally zoom in on data, which reduces the amount of data
transferredinto memory and speeds up the rate of data transfer. The digital
downconverterdoes this by frequency-translating, filtering, and decimating
signals after theygo throu gh the ADC. See the Incorporating the DDC
section for more information.
The PLL uses a phase dectetor to synchronize the acquisition clock to
either a 10 MHz reference clock supplied through REF CLK IN or to the
CLK 10s ignalfrom the PXI backplane. You can also choose to leave the
TIO
(Timingand Control)
Digital
Downconverter
Voltage
Controlled
Oscillator
P
X
I
DataPath
Logic
Onboard
Memory
Filter
MITE
(PXIInterface)
ADC
Dither
+
Analog
Input
(INPUT)
Triggerand
ClockRouting
10MHz
Reference
Input
(REFCLK IN)
EXTTRIG
(PFI)
ExternalTrigger PXITrigger
CLK10
Phase
Detector
CalDAC
PLL