Memory
Each channel pair operates in lockstep; that is, a single cache line is stored across two DIMMs with each DIMM on a different channel of the lockstep pair.
yEight fully buffered DIMM slots for each channel. A cell with two memory boards contains 32 DIMM slots.
yDouble Data Rate 2
yDIMM capacities of 2 GB or 4 GB.
y
Figure
Figure 2-4 Memory Boards
DIMM Slot Numbering
Figure