NXP Semiconductors TFA9812

TFA9812_2 © NXP B.V. 2009. All rights reserved.

Preliminary data sheet Rev. 02 — 22 January 2009 25 of 66

NXP Semiconductors TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

8.7.6 Overdissipation protection

When the output current of the power ampliﬁers exceeds a current value of 3 A and the

temperature is above 140 °C, overdissipation protection is activated and the device enters

Sleep mode. A restart will be initiated automatically when the two overdissipation

conditions are both changed to ‘false’.

Overdissipation is ﬂagged by a low DIAG pin and by a high DIAG I2C status bit, see

Section 9.5.10.

Under normal conditions thermal foldback prevents overdissipation protection from being

triggered. I2C settings remain valid.

8.7.7 Window protection

Window protection is a feature for protecting the device against shorts from the outputs to

the ground or supply lines. If during power-up one of the outputs is shorted to VSSPx or

VDDP, power-up does not proceed any further. The trigger levels for these conditions are:

•OUTxx > VDDA − 1 V, or

•OUTxx < REFA + 1 V.

The WP alarm is ﬂagged by a low DIAG pin and by a high DIAG I2C status bit, see

Section 9.5.10.

8.7.8 Lock protection

When the selected clock input source (MCLK, BCK or crystal) stops running, the TFA9812

is able to detect this and set the output stages to 3-state mode. Without this protection

peripheral devices in an application might be damaged.

The PLL lock indication is an I2C reading and will be ‘false’ in the event of a clock

interruption, see Section 9.5.10.

8.7.9 Underfrequency protection

UFP sets the output stages to 3-state mode when the clock input source is too low. The

PWM switching frequency can becomes critically low when the clock input source is lower

than speciﬁed. Without UFP peripheral devices in an application might be damaged.

The status of the UFP is shown in I2C reading register, see Section 9.5.10.

8.7.10 Overfrequency protection

OFP sets the output stages to 3-state mode when the clock input source is too high. The

PWM controller can become unstable when the clock input source is higher than

speciﬁed. Without OFP peripheral devices in an application might be damaged.

The status of the OFP is shown in I2C reading register, see Section 9.5.10.

Table 20. Undervoltage trigger levels

Pin name UVP level DIAG pin (protection active)

Min Max

VDDA ≥ 7 V < 8 V LOW

VDDA(3V3) ≥ 1.6 V < 3 V -

Contents

Main 1. General description 2. Features 2.1 General features TFA9812 Rev. 02 22 January 2009 Preliminary data sheet BTL stereo Class-D audio amplier with I2S input NXP Semiconductors TFA9812 2.2 DSP features 3. Applications 4. Quick reference data =12V,V =0V,V = 3.3 V, ,f 5. Ordering information 6. Block diagram Fig 1. TFA9812 block diagram TFA9812 Preliminary data sheet Rev. 02 22 January 2009 6 of 66 7. Pinning information 7.1 Pinning 4 STABA O 1.8 V analog stabilizer output 5 REFA P Analog reference voltage 6V 7 TEST1 I T est signal input 1. F or test pur poses only (connect to V 8V TFA9812HN Page NXP Semiconductors TFA9812 8. Functional description 8.1 General Page 8.2.3 I2S master/slave modes and MCLK/BCK clock modes Page NXP Semiconductors TFA9812 8.3 Power-up/power-down 8.3.1 Power-up 8.3.2 Power-down 8.4 Digital audio data input 8.4.1 Digital audio data format support Remark: Only MSB-rst formats are supported. TFA9812_2 NXP B.V. 2009. All rights reserved. Fig 4. Serial interface input and output formats control mode 8.4.2 Digital audio data format control 8.5 Digital signal-processing features 8.5.1 Equalizer Page Page Preliminary data sheet Rev. 02 22 January 2009 20 of 66 8.5.2 Digital volume control Fig 7. T ransfer functions f or several center frequencies f Fig 8. Transfer functions for several gain factors G 8.5.3 Soft mute and mute 8.5.4 Output signal and word-select polarity control 8.5.5 Gain boost and clip level control 8.5.6 Output power limiter 8.5.7 PWM control for performance improvement Page 8.7.1 Thermal foldback 8.7.2 Overtemperature protection 8.7.3 Overcurrent protection 8.7.4 Overvoltage protection 8.7.5 Undervoltage protections 8.7.8 Lock protection 8.7.9 Underfrequency protection 8.7.10 Overfrequency protection 8.7.11 Invalid BCK protection 8.7.12 DC blocking 8.7.13 Overview protections Table 21 shows the overview of the protections. 9. I2C bus interface and register settings 9.1 I2C bus interface Voltage values applied to the I2C bus device address pins are interpreted as described in Table 23. 9.2 I2C bus TFA9812 device addresses 9.3 I2C write cycle description 9.4 I2C read cycle description 9.5 Top-level register map Reserved registers or bits will be indicated by RSD. 9.5.1 Interpolator settings and soft mute 9.5.2 Volume control 9.5.3 Digital input format 9.5.4 Equalizer conguration 9.5.5 Equalizer settings For word1 for equalizer 'yy' see Figure 9 For word2 for equalizer 'yy' see Figure 9 Page 9.5.6 PWM signal control 9.5.7 Digital-in clock conguration 9.5.8 Thermal foldback control 9.5.9 TFA9812 temperature 9.5.10 Miscellaneous status 9.6 Overview of functional control in each control mode D = xed control setting, determined by default I 10. Internal circuitry D = xed control setting, determined by default I Page Page 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). 12. Thermal characteristics In accordance with the Absolute Maximum Rating System (IEC 60134). 13. Characteristics 13.1 DC Characteristics = 400 kHz, 24-bit I = V = 0 V, V Page Page 13.2 AC characteristics < 0.1 = 3.3 V, T , R , f 13.3 Timing 14. Application information 14.1 Output power estimation 14.2 Output current limiting 14.3 Speaker conguration and impedance 14.4 Typical application schematics 14.4.1 I2S slave mode and Legacy control mode Fig 13. Simplied application diagram for I2S slave mode and Legacy control mode 14.4.2 I2S slave mode and I2C control mode Fig 14. Simplied application diagram for I2S slave mode and I2C control mode 14.4.3 I2S master mode and Legacy control mode Fig 15. Simplied application diagram for I2S master mode and Legacy control mode 14.4.4 I2S master mode and I2C control mode Fig 16. Simplied application diagram for I2S master mode and I2C control mode 14.5 Curves measured in typical application a. VP = 12 V; RL = 2 6 b. VP = 12 V; RL = 2 8 VP = 12 V; PO = 1 W (1) RL = 6 15 H / 680 F (2) RL = 8 15 H / 680 F Fig 19. Gain as a function of frequency Fig 20. Gain as a function of AVOL VP = 12 V; RL = 8 ; fi = 1 kHz (1) 0 dB (2) 24 dB gain boost VP = 12 V; Vripple = 500 mV (RMS) reference to ground; No input signal (1) RL = 8 (2) RL = 6 Fig 21. SVRR as a function of frequency Fig 22. S/N ratio as a function of output power VP = 15 V; 20 kHz AES17 lter (1) RL = 2 8 (2) RL = 2 6 Fig 23. Output power as a function of time a. VP = 15 V; RL = 2 6 BTL; fi = 1 kHz b. VP = 20 V; RL = 2 8 BTL; fi = 1 kHz (1) Tact(th_fold) = 125 C (2) Tact(th_fold) = 105 C (3) Tact(th_fold) = 90 C a. VP = 12 V; RL = 2 6 ; fi = 1 kHz; THD = 1 % b. VP = 12 V; RL = 2 6 ; fi = 1 kHz; THD = 10 % VP = 12 V; fi = 1 kHz; Power dissipation in junction only VP = 12 V; fi = 1 kHz; po = (2 Po) / (2 Po + Pd) VP = 12 V; PO = 1 W Fig 27. Channel separation as a function of frequency 15. Package outline Fig 28. Package outline SOT619-8 (HVQFN48) SOT619-8 Page 17. Revision history 18. Legal information 18.1 Data sheet status 18.2 Denitions 18.3 Disclaimers 18.4 Trademarks 20. Contents