TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 33 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input

9.5.5 Equalizer settings

[1] Default settings are shown in Table 27. The corresponding equalizer configuration is shown in Table 40.
[1] Default settings are shown in Table 27. The corresponding equalizer configuration is shown in Table 40.
Table 35. Bit description of register 03h: equalizer configuration
Bit Symbol Description
1 EQ_BP Equalizer bypass enable:
0 = Equalizer not bypassed
1 = Equalizer bypassed
0 EQ_BND Equalizer 10-band or 5-band configuration selection:
0 = 10-band equalizer configuration enabled
1 = 5-band equalizer configuration enabled
Table 36. Register addresses xxh = 04, 06...2A

For word1 for equalizer 'yy' see Figure 9

Bit 15 14 13 12 11 10 9 8
Symbol Eyy_t1Eyy_k1m10 Eyy_k1m9 Eyy_k1m8 Eyy_k1m7 Eyy_k1m6 Eyy_k1m5 Eyy_k1m4
Default[1] --------
Bit 76543210
Symbol Eyy_k1m3 Eyy_k1m2 Eyy_k1m1 Eyy_k1m0 Eyy_k1e3 Eyy_k1e2 Eyy_k1e1 Eyy_k1e0
Default[1] --------
Table 37. Register addresses xxh = 05, 07...2B

For word2 for equalizer 'yy' see Figure 9

Bit 15 14 13 12 11 10 9 8
Symbol Eyy_t2Eyy_k2m3 Eyy_k2m2 Eyy_k2m1 Eyy_k2m0 Eyy_k2e2 Eyy_k2e1 Eyy_k2e0
Default --------
Bit 76543210
Symbol Eyy_k06 Eyy_k05 Eyy_k04 Eyy_k03 Eyy_k02 Eyy_k01 Eyy_k00 Eyy_s
Default --------