NXP Semiconductors TFA9812 8.7.11 Invalid BCK protection, 8.7.12 DC blocking, 8.7.13 Overview protections

TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 26 of 66
NXP Semiconductors TFA9812
BTL stereo Class-D audio amplifier with I2S input
8.7.11 Invalid BCK protection
The BCK clock signal is verified as being at one of the allowed relative frequencies: 32 fs,
48 fsor 64 fs. If it is not at one of these frequencies the TFA9812 will set the output stages
to 3-state mode to prevent audible effects.
The MCLK clock signal is also verified as being valid, see Section 8.2.3.
Detection of violation results in an automatic internal overruling of the MCLK assignment
to BCK.
8.7.12 DC blocking
The TFA9812 features a high pass filter after the I2S input to block DC signals. DC values
at the output can damage the peripheral devices. The high pass filter is always enabled.
8.7.13 Overview protections
Table 21 shows the overview of the protections.
Table 21. Overview protections
Protections
Symbol Conditions DIAG
pin I2C flag[1] Output Recovering
TF programmable
max. Tj> 125 °CFloating - Switching Automatic, increasing
volume control back to
volume setting
OTP Tj > 160 °C LOW DIAG Floating Automatic, after 1 µs and
Tj< 160 °C
OCP IO > IORM LOW DIAG Floating Automatic, after 1 µs and
IO<I
ORM
OVP VDDA > 20 V LOW DIAG Floating Restart (fault to operating
when VDDA > 8 V and
VDDA(3V3) >3V)
UVP VDDA < 8 V or
VDDA(3V3) <3V LOW DIAG Floating Restart (fault to operating
when VDDA > 8 V and
VDDA(3V3) >3V)
ODP Tj> 140 °C and IO>I
ORM LOW DIAG Floating Restart (fault to operating
when Tj< 140 °C or
IO < IORM)
WP[2] OUTX > VDDA −1 V or
OUTX < REFA + 1 V LOW DIAG Floating Restart (fault to operating when OUTX < VDDA −1V
and OUTX > VSSA +1V)
LP PLL out of lock Floating LP Floating Restart (fault to operating
when PLL is in lock)
UFP PLL frequency < 45 MHz Floating UFP Floating Restart (fault to operating
when
PLL frequency > 45 MHz)