Omron C200HS 113, Programming Precautions Section 4-10

113

Except for instructions for which conditions are not allowed (e.g., INTERLOCK

CLEAR and JUMP END, see below), every instruction line must also have at

least one condition on it to determine the execution condition for the instruction

at the right. Again, diagram A , below, must be drawn as diagram B. If an instruc-

tion must be continuously executed (e.g., if an output must always be kept ON

while the program is being executed), the Always ON Flag (SR 25313) in the SR

area can be used.

Instruction

25313

Instruction

Diagram A: Incorrect

Diagram B

Address Instruction Operands

00000 LD 25313

00001 Instruction

There are a few exceptions to this rule, including the INTERLOCK CLEAR,

JUMP END, and step instructions. Each of these instructions is used as the sec-

ond of a pair of instructions and is controlled by the execution condition of the

first of the pair. Conditions should not be placed on the instruction lines leading to

these instructions. Refer to

Section 5 Instruction Set

for details.

When drawing ladder diagrams, it is important to keep in mind the number of

instructions that will be required to input it. In diagram A, below, an OR LOAD

instruction will be required to combine the top and bottom instruction lines. This

can be avoided by redrawing as shown in diagram B so that no AND LOAD or OR

LOAD instructions are required. Refer to

5-8-2

AND LOAD and OR LOAD

for

more details and

Section 7 Program Monitoring and Execution

for further exam-

ples.

00000

00001 00207

00207

00001

00000

00207 00207

Diagram A

Diagram B

Address Instruction Operands

00000 LD 00000

00001 LD 00001

00002 AND 00207

00003 OR LD ---

00004 OUT 00207

Address Instruction Operands

00000 LD 00001

00001 AND 00207

00002 OR 00000

00003 OUT 002

Programming Precautions Section 4-10

Contents

Main Page ii Notice: 1, 2, 3... DANGER WARNING OMRON Product References About this Manual: WARNING v TABLE OF CONTENTS SECTION 2 Hardware Considerations 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . vi SECTION 4 Writing and Inputting the Program 63 . . . . . . . . . . . . . . . . . . vii viii ix x SECTION 6 Program Execution Timing 317 . . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 7 Program Monitoring and Execution 345 . . . . . . . . . . . . . . . . . . SECTION 8 Communications 373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 9 Memory Cassette Operations 385 . . . . . . . . . . . . . . . . . . . . . . . . xi SECTION 11 Host Link Commands 401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page xiii PRECAUTIONS xiv Operating Environment Precautions 4 1 Intended Audience 2 General Precautions WARNING 3 Safety Precautions WARNING 5 Application Precautions WARNING Page SECTION 1 Introduction 2 The Origins of PC Logic Section 1-2 1-1 Overview 1-2 The Origins of PC Logic 4-4 Basic Ladder Diagrams 3 OMRON Product Terminology Section 1-4 1-3 PC Terminology Standard Models Appendix A Glossary Sec- tion 2 Hardware Considerations 1-5 Overview of PC Operation 5 Available Manuals Section 1-7 Operation Manuals Operation Guides 1-6 Peripheral Devices 1-7 Available Manuals 1-8 New C200HS Features 1-8-1 Improved Memory Capabilities 1-8-2 Faster Execution Times 1-8-3 Larger Instruction Set 1-8-4 Wide Selection of Special I/O Units 1-8-5 Improved Interrupt Functions 1-8-6 SYSMAC NET Link and SYSMAC LINK Capabilities 1-8-7 Built-in RS-232C Connector 1-8-8 More Flexible PC Settings 1-8-9 Debugging and Maintenance 1-8-10 New Programming Console Operations 1-8-11 Peripheral Devices 1-8-12 Using C200H Programs Page Page Page 16 CPU Components Section 2-1 2-1 CPU Components 17 CPU Components Section 2-1 C200HS-CPU21-E/CPU23-E/CPU31-E/CPU33-E COMM 2-1-1 CPU Indicators 18 PC Configuration Section 2-2 2-1-2 Peripheral Device Connection 3-3 IR Area. 2-2 PC Configuration 19 CPU Capabilities Section 2-3 C200HS Installation Guide 2-3 CPU Capabilities 20 Memory Cassettes Section 2-4 2-4 Memory Cassettes 2-5 Installing Memory Cassettes 21 Installing Memory Cassettes Section 2-5 2-5 Installing Memory Cassettes 2-4 Memory Cassettes Page 23 CPU DIP Switch Section 2-6 2-6 CPU DIP Switch SECTION 3 Memory Areas 26 Introduction Section 3-1 3-1 Introduction Section 4 Writing and Input- ting the Program 3-2 Data Area Structure 5-14 Timer and Counter Instructions 3-8 TC Area 3-8 TC Area 5-18 Data Conversion 29 Signed and Unsigned Binary Data Reverse the procedure to convert negative signed binary data to decimal. 1. First take the absolute value (12345) and convert to unsigned binary: 2. Next take the complement: 3. Finally add one: Converting Decimal to Signed Binary 3-3 IR (Internal Relay) Area 5-15-1 Shift Register SFT(10) 32 IR Area Section 3-3 3-4 SR (Special Relay) Area Page Page Page 3-4-1 SYSMAC NET/SYSMAC LINK System Loop Status SR 236 provides the local node loop status for SYSMAC NET Systems, as shown below. SYSMAC LINK SYSMAC NET 3-4-2 Remote I/O Systems Optical Wired Re- mote I/O System Manuals 3-4-3 Link System Flags and Control Bits 40 Host Link Systems PC Link System Manual Host Link System Manual PC Link Systems 3-4-4 Forced Status Hold Bit 3-4-5 I/O Status Hold Bit 3-4-6 Output OFF Bit 3-4-7 FAL (Failure Alarm) Area 3-4-8 Low Battery Flag 3-4-9 Cycle Time Error Flag 3-4-10 I/O Verification Error Flag 5-14 Timer and Counter Instructions 3-4-11 First Cycle Flag 5-14 Timer and Counter Instructions 3-4-13 Step Flag 3-4-14 Group-2 Error Flag 5-20 Binary Calculations 5-19 BCD Calculations 5-17 Data Comparison 3-4-18 Interrupt Subroutine Areas 3-4-19 RS-232C Port Communications Areas 3-4-20 Peripheral Port Communications Areas 3-4-21 Memory Cassette Areas 3-4-22 Data Transfer Error Bits 3-4-23 Ladder Diagram Memory Areas 3-4-24 Memory Error Flags 3-4-25 Data Save Flags 3-4-26 Transfer Error Flags 3-5 AR (Auxiliary Relay) Area Page 3-5-1 Restarting Special I/O Units 3-5-2 Slave Rack Error Flags 3-5-3 Group-2 Error Flags 3-5-4 Optical I/O Unit and I/O Terminal Error Flags 3-5-5 SYSMAC LINK System Data Link Settings 3-5-6 Error History Bits 3-6 DM Area 3-5-7 Active Node Flags 3-5-8 SYSMAC LINK/SYSMAC NET Link System Service Time 3-5-9 Calendar/Clock Area and Bits 3-5-10 TERMINAL Mode Key Bits 3-5-11 Power OFF Counter 7-1-4 Hexadecimal/BCD Data Modification 5-25-3 TRACE MEMORY SAMPLING TRSM(45) 5-25-12 FAILURE POINT DETECT FPD() 3-5-14 CPU-mounting Device Mounted Flag 3-6 DM (Data Memory) Area 3-6-1 Expansion DM Area 1-8-10 New Programming Console Operations 3-6-2 Special I/O Unit Data 3-6-4 PC Setup 3-6-3 Error History Area Section 10 Troubleshooting 3-6-4 PC Setup Appen- dix E PC Setup The PC Setup is allocated to DM 6600 through DM 6655. 60 TC Area Section 3-8 3-7 HR (Holding Relay) Area Section 5 Instruc- tion Set 3-8 TC (Timer/Counter) Area 7-1 Monitoring Operation and Modifying Data. 5-10 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) 3-9 LR (Link Relay) Area PC Link System Manual 5-10 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) 3-10 UM Area 3-11 TR (Temporary Relay) Area SECTION 4 Writing and Inputting the Program 64 Instruction Terminology Section 4-2 4-1 Basic Procedure 4-2 Instruction Terminology 4-3 Program Capacity 3-10 UM Area 4-4 Basic Ladder Diagrams 4-4-1 Basic Terms 4-7-7 Branching Instruction Lines 4-4-2 Mnemonic Code 4-4-3 Ladder Instructions Page Page 4-4-4 OUTPUT and OUTPUT NOT 4-4-5 The END Instruction 4-4-6 Logic Block Instructions Page Page Page Page Page Page 78 The Programming Console Section 4-5 4-4-7 Coding Multiple Right-hand Instructions 5-25-6 TERMINAL MODE TERM() 4-5 The Programming Console 4-7 Inputting, Modifying, and Checking the Program 4-5-1 The Keyboard 79 The Programming Console Section 4-5 80 4-5-2 PC Modes DANGER 4-6 Preparation for Operation DANGER 4-6-1 Entering the Password 4-6-3 Clearing Memory 4-6-1 Entering the Password 4-6-2 Buzzer 4-6-3 Clearing Memory Page 4-6-4 Registering the I/O Table 4-6-5 Clearing Error Messages Section 10 Troubleshoot- ing 4-6-6 Verifying the I/O Table 4-6-7 Reading the I/O Table 88 Meaning of Displays I/O Units Mounted in Remote Slave Racks 4-6-8 Clearing the I/O Table 4-6-9 SYSMAC NET Link Table Transfer (CPU31/33-E Only) Page 4-7 Inputting, Modifying, and Checking the Program 4-7-1 Setting and Reading from Program Memory Address 4-7-2 Entering and Editing Programs Page Page 4-7-3 Checking the Program Many of the following errors are for instructions that have not yet been described yet. Refer to or to 4-8 Controlling Bit Status for details on these. 4-7-4 Displaying the Cycle Time Section 6 Program Execution Timing 4-7-5 Program Searches 4-7-6 Inserting and Deleting Instructions Page Page 4-7-7 Branching Instruction Lines Page Page 5-10 INTER- LOCK and INTERLOCK CLEAR IL(02) and ILC(03). 4-7-8 Jumps 108 Controlling Bit Status Section 4-8 4-8 Controlling Bit Status 5-9 Bit Control Instructions 109 Controlling Bit Status Section 4-8 4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN 4-8-2 KEEP 4-8-3 Self-maintaining Bits (Seal) 110 Work Bits Section 4-9 4-9 Work Bits (Internal Relays) 5-15-1 SHIFT REGISTER SFT(10) 111 Work Bits Section 4-9 112 Programming Precautions Section 4-10 4-10 Programming Precautions 113 Programming Precautions Section 4-10 AND LOAD and OR LOAD 5-8-2 114 4-11 Program Execution Section 6 Program Execution Timing SECTION 5 Instruction Set Page Page 118 Data Areas, Definer Values, and Flags Section 5-3 5-1 Notation Limitations Section 3 Memory Areas Section 5-4 Appendix B 5-4 Differentiated Instructions 120 Expansion Instructions Section 5-5 5-10 INTERLOCK and INTERLOCK CLEAR IL(02) and IL(03) 7-1-14 Expansion Instruction Function Code Assignments 5-5 Expansion Instructions 121 Expansion Instructions Section 5-5 5-6 Coding Right-hand Instructions Section 4 Writing and Inputting the Program The following diagram and corresponding mnemonic code illustrates the points described above. Page 5-7 Instruction Set Lists e 5-5 Expansion Instructions for a list of the expansion instructions. 5-7-1 Function Codes Page Page Page 129 Ladder Diagram Instructions Section 5-8 5-8 Ladder Diagram Instructions 4-4-3 Ladder Instructions 5-8-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT 5-8-2 AND LOAD and OR LOAD 4-7 5-9 Bit Control Instructions 5-9-1 OUTPUT and OUTPUT NOT OUT and OUT NOT 4-7-7 Branching Instruction Lines 5-9-2 DIFFERENTIATE UP and DOWN DIFU(13) and DIFD(14) Precautions 5-10 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) 5-11 JUMP and JUMP END JMP(04) and JME(05) 5-23 Subroutines and Inter- rupt Control 5-9-3 SET and RESET SET and RSET 5-9-4 KEEP KEEP(11) 134 4-8-3 Self-maintain- ing Bits NEVER 5-10 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) 135 5-10 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) 4-7-7 Branching Instruction Lines 136 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) Section 5-10 137 JUMP and JUMP END JMP(04) and JME(05) Section 5-11 5-11 JUMP and JUMP END JMP(04) and JME(05) 4-7-8 Jumps 5-12 END END(01) 5-13 NO OPERATION NOP(00) 5-14 Timer and Counter Instructions 5-14-1 TIMER TIM 5-14-2 HIGH-SPEED TIMER TIMH(15) Page 5-14-4 COUNTER CNT 5-9-4 KEEP KEEP(11) Page 5-14-2 HIGH-SPEED TIMER TIMH(15) 5-14-4 COUNTER CNT 5-14-3 TOTALIZING TIMER TTIM(87) 5-14-4 COUNTER CNT Page Page 5-14-5 REVERSIBLE COUNTER CNTR(12) Page 5-15 Data Shifting 5-15-1 SHIFT REGISTER SFT(10) Example 2: Controlling Bits in Shift Registers Page 5-15-2 REVERSIBLE SHIFT REGISTER SFTR(84) Limitations St and E must be in the same data area and St must be less than or equal to E. Page 5-15-3 ARITHMETIC SHIFT LEFT ASL(25) 5-15-4 ARITHMETIC SHIFT RIGHT ASR(26) 5-15-5 ROTATE LEFT ROL(27) 5-15-6 ROTATE RIGHT ROR(28) 5-15-7 ONE DIGIT SHIFT LEFT SLD(74) ... 5-15-8 ONE DIGIT SHIFT RIGHT SRD(75) 5-15-9 WORD SHIFT WSFT(16) 5-15-10 ASYNCHRONOUS SHIFT REGISTER ASFT(17) Example 5-16 Data Movement 5-16-1 MOVE MOV(21) 5-16-2 MOVE NOT MVN(22) 5-16-3 BLOCK SET BSET(71) 5-16-4 BLOCK TRANSFER XFER(70) N: Number of words (BCD) S: Starting source word D: Starting destination word XFER(70) 5-16-5 DATA EXCHANGE XCHG(73) 5-16-6 SINGLE WORD DISTRIBUTE DIST(80) 5-16-7 DATA COLLECT COLL(81 5-16-7 DATA COLLECT COLL(81) 5-16-6 SINGLE WORD DISTRIBUTE DIST(80 5-16-6 SINGLE WORD DISTRIBUTE (80 EQ: ON when the transferred data is zero; otherwise OFF. 5-16-8 MOVE BIT MOVB(82) S: Source word IR, SR, AR, DM, HR, LR, # Bi: Bit designator (BCD) D: Destination word MOVB(82) Bi 5-16-9 MOVE DIGIT MOVD(83) Digit Designator The following show examples of the data movements for various values of Di. Note 255 (FF) bits or more can not be copied at one time. 5-16-10 TRANSFER BITS XFRB(62) C: Control word IR, SR, AR, DM, TC, HR, LR, # S: First source word XFRB(62) @XFRB(62) 5-17 Data Comparison 5-17-1 MULTI-WORD COMPARE MCMP(19) 5-17-2 COMPARE CMP(20) 5-17-8 SIGNED BINARY COMPARE CPS() Page 5-17-3 DOUBLE COMPARE CMPL(60) Cp2: First word of second compare word pair Cp1: First word of first compare word pair IR, SR, AR, DM, HR, TC, TR CMPL(60) Cp1 Cp2 ___ 5-17-9 DOUBLE SIGNED BINARY COMPARE CPSL() 5-17-4 BLOCK COMPARE BCMP(68) 5-17-5 TABLE COMPARE TCMP(85) 5-17-6 AREA RANGE COMPARE ZCP(88) 5-17-7 DOUBLE AREA RANGE COMPARE ZCPL() 5-17-6 AREA RANGE COMPARE ZCP(88) 5-17-8 SIGNED BINARY COMPARE CPS() 5-17-2 Compare CMP(20) 5-17-9 DOUBLE SIGNED BINARY COMPARE CPSL() 5-17-2 Compare CMP(20) 5-18 Data Conversion 5-18-1 BCD-TO-BINARY BIN(23) 5-18-2 DOUBLE BCD-TO-DOUBLE BINARY BINL(58) 5-18-3 BINARY-TO-BCD BCD(24) 5-18-4 DOUBLE BINARY-TO-DOUBLE BCD BCDL(59) 5-18-5 HOURS-TO-SECONDS SEC(65) 5-18-6 SECONDS-TO-HOURS HMS(66) 5-18-7 4-TO-16 DECODER MLPX(76) Page Page 5-18-8 16-TO-4 ENCODER DMPX(77) Example: 4-bit to 16-bit Decoding Page Page 5-18-9 7-SEGMENT DECODER SDEC(78) S: Source word (binary) Di: Digit designator SDEC(78) Di Page Flags ER: Incorrect digit designator, or data area for destination exceeded 5-18-10 ASCII CONVERT ASC(86) Appendix I 5-18-11 ASCII-TO-HEXADECIMAL HEX() Page Appendix I for a table of ASCII characters. 5-18-12 SCALING SCL() Page 5-18-13 COLUMN TO LINE LINE(63) 5-18-14 LINE TO COLUMN COLM(64) 5-18-15 2S COMPLEMENT NEG() 5-18-16 DOUBLE 2S COMPLEMENT NEGL() 5-19 BCD Calculations 5-19-1 INCREMENT INC(38) 5-19-2 DECREMENT DEC(39) 205 5-19-3 SET CARRY STC(40) Appendix C Error and Arithmetic Flag Operation 5-19-4 CLEAR CARRY CLC(41) 5-19-5 BCD ADD ADD(30) Au + Ad + CY CY R + 207 5-20-1 BINARY ADD ADB(50) 5-19-7 BCD SUBTRACT SUB(31) Mi Su CY CY R Page 5-19-8 DOUBLE BCD SUBTRACT SUBL(55) 5-16-3 BLOCK SET BSET(71) Flags ER: Mi, M+1,Su, or Su+1 are not BCD. First subtraction Second subtraction Turned ON to indicate negative result. 5-19-9 BCD MULTIPLY MUL(32) 5-19-10 DOUBLE BCD MULTIPLY MULL(56) x 5-19-11 BCD DIVIDE DIV(33) 5-19-12 DOUBLE BCD DIVIDE DIVL(57) 5-19-13 FLOATING POINT DIVIDE FDIV(79) Page 0.4369620 x 10 5-19-14 SQUARE ROOT ROOT(72) In this example, 6017 = 77.56, and 77.56 is rounded off to 78. 5600 > 4900 219 5-20 Binary Calculations 5-19 BCD Calculations 5-20-1 BINARY ADD ADB(50) Au + Ad + CY CY R Page 221 5-20-2 BINARY SUBTRACT SBB(51) Mi Su CY CY R Page Page 5-20-3 BINARY MULTIPLY MLB(52) 5-20-7 SIGNED BINARY MULTIPLY MBS() 5-20-4 BINARY DIVIDE DVB(53) 5-20-9 SIGNED BINARY DIVIDE DBS() 5-20-5 DOUBLE BINARY ADD ADBL() + Page 5-20-6 DOUBLE BINARY SUBTRACT SBBL() Page 5-20-7 SIGNED BINARY MULTIPLY MBS() 5-20-8 DOUBLE SIGNED BINARY MULTIPLY MBSL() x 5-20-9 SIGNED BINARY DIVIDE DBS() 5-20-10DOUBLE SIGNED BINARY DIVIDE DBSL() 5-21 Special Math Instructions 5-21-1 FIND MAXIMUM MAX() 5-21-2 FIND MINIMUM MIN() 5-21-3 AVERAGE VALUE AVG() Page 5-21-4 SUM SUM() C: Control data R1: First word in range SUM() R Page 5-21-5 ARITHMETIC PROCESS APR(69) 240 Examples C: Input data, x Result data Input data, x Result data C+(2m+1) X C+(2m+2) Y 5-21-6 PID CONTROL PID() Page Page Page Page Page Page 5-22 Logic Instructions Example EQ: ON when the result is 0. 5-22-1 COMPLEMENT COM(29) Wd: Complement word 5-22-2 LOGICAL AND ANDW(34) 5-22-3 LOGICAL OR ORW(35) 5-22-4 EXCLUSIVE OR XORW(36) 5-22-5 EXCLUSIVE NOR XNRW(37) 5-23 Subroutines and Interrupt Control 5-23-1 Subroutines 5-23-2 Interrupts 5-23-5 MACRO MCRO(99) 5-23-2 Interrupts Page Page 5-23-3 SUBROUTINE ENTER SBS(91) Page 5-23-4 SUBROUTINE DEFINE and RETURN SBN(92)/RET(93) 5-23-5 MACRO MCRO(99) Page 5-23-6 INTERRUPT CONTROL INT(89) Page Page Page 5-24 Step Instructions 5-24-1 STEP DEFINE and STEP STARTSTEP(08)/SNXT(09) Page 268 Examples Page Page Page Page Page Page 5-25 Special Instructions 5-25-1 FAILURE ALARM FAL(06) and SEVERE FAILURE ALARM FALS(07) 4-6-5 Clearing Error Messages 5-25-2 CYCLE TIME SCAN(18) 5-25-3 TRACE MEMORY SAMPLING TRSM(45) Operation Manual LSS 5-25-4 MESSAGE DISPLAY MSG(46) Appendix I 4-6-5 Clearing Error Messages 5-25-5 LONG MESSAGE LMSG(47) 5-25-6 TERMINAL MODE TERM(48) Example 5-25-6 TERMINAL MODE TERM(48) 5-25-7 WATCHDOG TIMER REFRESH WDT(94) 5-25-8 I/O REFRESH IORF(97) 5-25-9 GROUP-2 HIGH-DENSITY I/O REFRESH MPRF(61) 6-1 Cycle Time 5-25-9 GROUP-2 HIGH-DENSITY I/O REFRESH MPRF(61) 6-1 Cycle Time 5-25-10 BIT COUNTER BCNT(67) 5-25-11 FRAME CHECKSUM FCS() Page 5-25-12 FAILURE POINT DETECTION FPD() Page Page Page 5-25-13 DATA SEARCH SRCH() 5-25-14 EXPANSION DM READ XDMR() 7-1-15 UM Area Allocation 5-26 Network Instructions 5-26-1 NETWORK SEND SEND(90) 292 Control Data SYSMAC NET Link System Manual for details. SYSMAC LINK Systems Set the destination node number to 0 to send the data to all nodes. Refer to the 5-26-2 NETWORK RECEIVE RECV(98) Control Data SYS- MAC NET Link System Manual SYSMAC LINK Systems Refer to the for details. There is no SYSMAC NET Link/SYSMAC LINK Unit. 5-26-3 About Network Communications SYSMAC NET Link System Manual Page 5-27 Serial Communications Instructions 5-27-1 RECEIVE RXD() C: Control word N: Number of bytes RXD() Page 5-27-2 TRANSMIT TXD() Page 5-28 Advanced I/O Instructions 5-28-1 7-SEGMENT DISPLAY OUTPUT 7SEG() Page Page 5-28-2 DIGITAL SWITCH INPUT DSW() ID212 A7E data line rightmost digits Leftmost digits Interface A7E data line leftmost digits To A7E chip selection To A7E RD terminal Note An interface to convert signals from 5 V to 24 V is required to connect an A7E digital switch. The following example illustrates connections for an A7B Thumbwheel Switch. ID212 Input Unit Switch no. 8 76 5 4 32 1C A7B Thumbwheel Switch Page 5-28-3 HEXADECIMAL KEY INPUT HKY() ID212 Input Unit Page 5-28-4 TEN KEY INPUT TKY() Flags ER: Indirectly addressed DM word is non-existent. (Content of :DM word is 5-28-5 MATRIX INPUT MTR() Page Page SECTION 6 Program Execution Timing 6-1 Cycle Time Flowchart of CPU Operation Note A minimum cycle time can be set either in DM 6619 of the PC Setup or by executing SCAN(18). Page Page 322 Calculating Cycle Time Section 6-2 6-2 Calculating Cycle Time 6-3 Instruction Execution Times. 6-2-1 PC with I/O Units Only 323 Calculating Cycle Time Section 6-2 6-2-2 PC with Link Units 6-3 Instruction Execution Times Page Page Page Page Page Page Page Page 6-4 I/O Response Time 6-4-1 Basic Systems 6-4-2 Remote I/O Systems Page 6-4-3 Host Link Systems 6-4-4 PC Link Systems Page 6-4-5 One-to-one Link I/O Response Time Page 6-4-6 Interrupt Response Times Page Page SECTION 7 Program Monitoring and Execution 7-1 Monitoring Operation and Modifying Data 7-1-1 Bit/Word Monitor Page Page 7-1-2 Forced Set/Reset Page 7-1-3 Forced Set/Reset Cancel 7-1-4 Hexadecimal/BCD Data Modification 7-1-13 Changing Timer/Counter SV Page 7-1-5 Hex/ASCII Display Change 7-1-6 4-digit Hex/Decimal Display Change 7-1-7 8-digit Hex/Decimal Display Change 7-1-8 Differentiation Monitor 7-1-9 3-word Monitor 7-1-10 3-word Data Modification 7-1-11 Binary Monitor Page 7-1-12 Binary Data Modification 7-1-13 Changing Timer/Counter SV Page Page 7-1-14 Expansion Instruction Function Code Assignments 7-1-15 UM Area Allocation 7-1-16 Reading and Setting the Clock 7-1-17 Expansion Keyboard Mapping 7-1-18 Keyboard Mapping Page Page Page Page 8-1 Introduction 8-2 Parameters for Host Link and RS-232C Communications 8-2-1 Standard Communications Parameters 8-2-2 Specific Communications Parameters 8-2-3 Wiring Ports C200HS Installation Manual Section 11 8-2-4 Host Link Communications Host Link Commands. Page 8-2-5 RS-232C Communications Page Page 8-2-6 One-to-one Link Communications Page 8-2-7 NT Links Page 386 Memory Cassette Settings and Flags Section 9-2 9-1 Memory Cassettes C200HS Installation Guide 9-2 Memory Cassette Settings and Flags 387 UM Area Data Section 9-3 9-3 UM Area Data 388 IOM Area Data Section 9-4 9-4 IOM Area Data 389 IOM Area Data Section 9-4 Page 10-1 Alarm Indicators 2-1-1 CPU Indicators 7-1 Monitoring Operation and Modifying Data 10-2 Programmed Alarms and Error Messages 10-3 Reading and Clearing Errors and Messages Page 394 SYS FAIL FAL9A SYS FAIL FAL 9A SIOU ERR REMOTE ERR 395 * NO END INST MEMORY ERR I/O BUS ERR I/O UNIT OVER I/O SET ERROR SYS FAIL FAL** Section 4 Writing and Inputting the Program. 397 10-5 Error Flags and 3-4 SR Area 3-5 AR Area. SR Area 398 Error Flags Section 10-5 AR Area 399 Host Link Errors Section 10-6 10-6 Host Link Errors SECTION 11 Host Link Commands 402 Communications Procedure Section 11-1 11-1 Communications Procedure 403 Communications Procedure Section 11-1 Frame Transmission and Reception 11-2 Command and Response Formats 11-2-1 Commands from the Host Computer Page 11-2-2 Commands from the PC 11-3 Host Link Commands 11-3-1 IR/SR AREA READ RR 11-3-2 LR AREA READ RL 11-3-3 HR AREA READ RH The number of present values specified by the command is returned in hexade- Reads the contents of the specified number of HR words, starting from the speci- fied word. 11-3-4 PV READ RC 11-3-5 TC STATUS READ RG 11-3-6 DM AREA READ RD 11-3-7 AR AREA READ RJ 11-3-8 IR/SR AREA WRITE WR 11-3-9 LR AREA WRITE WL 11-3-10HR AREA WRITE WH 11-3-11PV WRITE WC 11-3-12TC STATUS WRITE WG 11-3-13DM AREA WRITE WD 11-3-14AR AREA WRITE WJ 11-3-15SV READ 1 R# 11-3-16SV READ 2 R$ 11-3-17SV READ 3 R% 11-3-18SV CHANGE 1 W# 11-3-19SV CHANGE 2 W$ 11-3-20SV CHANGE 3 W% 11-3-21STATUS READ MS 00 0 1 000 11-3-22STATUS WRITE SC Changes the PC operating mode. 000000 11-3-23ERROR READ MF Reads and clears errors in the PC. Also checks whether previous errors have been cleared. Error Information (Response) The error information comes in two words. 00 000 11-3-24FORCED SET KS 11-3-25FORCED RESET KR 11-3-26MULTIPLE FORCED SET/RESET FK Note Words 253 to 255 cannot be set when the CIO Area is specified. 11-3-27FORCED SET/RESET CANCEL KC 11-3-28PC MODEL READ MM 11-3-29TEST TS 11-3-30PROGRAM READ RP 427 11-3-31PROGRAM WRITE WP 11-3-32I/O TABLE GENERATE MI 11-3-33COMPOUND COMMAND QQ Registering Read Information , Batch Reading 11-3-34ABORT XZ 11-3-35INITIALIZE :: 11-3-36Undefined Command IC 431 Host Link Errors Section 11-4 11-4 Host Link Errors Appendix A Standard Models C200HS Racks Note: Units with lot numbers jjZ5 (Dec. 1995) or later. C200H Standard I/O Units C200H Group-2 High-density I/O Units C200H Group-2 B7A Interface Units C200H Special I/O Units Note For Read/Write Head and Data Carrier combinations, refer to the V600 FA ID System R/W Heads and EE- PROM Data Carriers Operation Manual and Supplement C200H Link Units SYSMAC LINK Unit/SYSMAC NET Link Unit Optional Products Mounting Rails and Accessories Link Adapters SYSMAC BUS/SYSMAC WAY Optical Fiber Products Plastic Clad Optical Fiber Cable/All Plastic Optical Fiber Cable Page SYSMAC LINK/SYSMAC NET Link Optical Fiber Products System Manual SYSMAC NET Link System Manual Programming Devices Training Materials Appendix B Programming Instructions Page Page Expansion Instructions Page Page Appendix C Error and Arithmetic Flag Operation Appendix CError and Arithmetic Flag Operation 450 Expansion Instructions Appendix CError and Arithmetic Flag Operation 451 Signed Binary Arithmetic Flags Page Appendix D Memory Areas Overview Note The PC Setup can be set to use DM 7000 through DM 7999 as the Special I/O Area. The following table shows the data areas in PC memory. SR Area Page Page Page AR Area DM Area (Error Log) Appendix E PC Setup Page Page Page Page 466 I/O Bits 467 Work Bits Page Page Page Page Appendix H Data Conversion Tables Normal Data Data Conversion Tables Appendix H 474 Signed Binary Data Appendix I Extended ASCII Programming Console Displays Glossary Page Page Page Page Page Page Page leftmost (bit/word). Page Page Page Page Page Page Page 493 Revision History 9-6 Host Link Errors 5-26-1 Network Instructions 4-6-9 SYSMAC NET Link Table Transfer 3-5-6 Active Node Flags Revision History 494 Revision code Revised contentDate Revision History About this Manual Special I/O Unit Refresh Precautions 495 Index A B C node number: sec8 378 E F programming example: 515 to 517 171 , 173 , 177 clearing: 518 to 519 205 setting: 518 to 519 205 See also host link precautions: sec11 405 I combining with OR: 41 to 46 69 combining with OR LD: 41 to 46 73 use in logic blocks: 41 to 46 72 using in interlocks: 51 to 514 136 using in jumps: 51 to 514 138 in controlling bit status: 47 on 109 J K L IL(02) and ILC(03): 47 on 105 using TR bits: 47 on 103 M N O P R onetoone link: sec8 382 procedures: sec8 379 receiving: sec8 381 transmitting: sec8 380 T TTIM(120): 51 to 514 145 U W