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Philips SC28L91 AC CHARACTERISTICS (3.3 VOL T)

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Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 14

AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3, 4

VCC = 3.3 V ± 10 %, Tamb = –40 °C to +85 °C, unless otherwise specified.

Symbol Parameter Min Typ Max Unit

Reset Timing (See Figure 4)

tRES Reset pulse width 100 20 ns

Bus Timing5 (See Figure 5)

t*AS A0–A3 setup time to RDN, WRN Low 10 6 ns

t*AH A0–A3 hold time from RDN, WRN low 33 ns

t*CS CEN setup time to RDN, WRN low 0 ns

t*CH CEN Hold time from RDN. WRN low 0 ns

t*RW WRN, RDN pulse width (Low time) 20 10 ns

t*DD Data valid after RDN low (125pF load. See Figure 3 for smaller loads.) 46 75 ns

t*DA RDN low to data bus active60 ns

t*DF Data bus floating after RDN or CEN high 15 20 ns

t*DI RDN or CEN high to data bus invalid70 ns

t*DS Data bus setup time before WRN or CEN high (write cycle) 43 ns

t*DH Data hold time after WRN high 0 –15 ns

t*RWD High time between read and/or write cycles5, 727 ns

Port Timing5 (See Figure 9)

t*PS Port in setup time before RDN low (Read IP ports cycle) 0 –20 ns

t*PH Port in hold time after RDN high 0 –20 ns

t*PD OP port valid after WRN or CEN high (OPR write cycle) 50 75 ns

Interrupt Timing (See Figure 10)

t*IR INTRN (or OP3–OP7 when used as interrupts) negated from:

Read RxFIFO (RxRDY/FFULL interrupt) 40 79 ns

Write TxFIFO (TxRDY interrupt) 40 79 ns

Reset Command (delta break change interrupt) 40 79 ns

Stop C/T command (Counter/timer interrupt) 40 79 ns

Read IPCR (delta input port change interrupt) 40 79 ns

Write IMR (Clear of change interrupt mask bit(s)) 40 79 ns

Clock Timing (See Figure 11)

t*CLK X1/CLK high or low time 35 25 ns

f*CLK X1/CLK frequency8 (for higher speeds contact factory) 0.1 3.686 8 MHz

f*CTC C/T Clk (IP2) high or low time (C/T external clock input) 30 15 ns

f*CTC C/T Clk (IP2) frequency8 (for higher speeds contact factory) 0 8 MHz

t*RX RxC high or low time (16X) 30 10 ns

f*RX RxC Frequency (16X) (for higher speeds contact factory) 0 16 MHz

RxC Frequency (1x)8, 90 1 MHz

t*TX TxC High or low time (16X) 30 15 ns

f*TX TxC frequency (16X) (for higher speeds contact factory) 16 MHz

TxC frequency (1X)8, 90 1 MHz

Transmitter Timing, external clock (See Figure 12)

t*TXD TxD output delay from TxC low (TxC input pin) 40 78 ns

t*TCS Output delay from TxC output pin low to TxD data output 8 30 ns

Contents

Main SC28L91 DESCRIPTION FEATURES Page 2004 Oct 21 4 PIN CONFIGURATION DIAGRAM 80XXX PIN CONFIGURATION Note: Pins marked No Connection must NOT be connected. SD00699 SD00698 3.3 V or 5.0 V Universal Asynchronous 2004 Oct 21 5 PIN CONFIGURATION DIAGRAM 68XXX PIN CONFIGURATION Note: Pins marked No Connection must NOT be connected. SD00701 2004 Oct 21 6 SD00702 Figure 1. Block Diagram (80XXX mode) 2004 Oct 21 7 SD00703 Figure 2. Block Diagram (68XXX mode) SC28L91 PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL) SC28L91 PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA) ABSOLUTE MAXIMUM RA TINGS DC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS (5 VOL T) Page AC CHARACTERISTICS (3.3 VOL T) Page Block Diagram Data Bus Buffer Operation Control Interrupt Control TIMING CIRCUITS Crystal Clock BRG Counter/Timer Timer Mode Counter Mode Timeout Mode Time Out Mode Caution Communications Input Port Output Port OPERATION Transmitter Receiver Transmitter Reset and Disable Receiver FIFO Receiver Status Bits Receiver Reset and Disable Watchdog Receiver Time-out Mode Watchdog and Time Out Mode Differences Multi-drop Mode (9-bit or Wake-Up) PROGRAMMING Table 1. SC28L91 register addressing Table 2. Condensed Register bit formats REGISTER DESCRIPTIONS MODE REGISTERS MR0 Mode Register 0 Table 3. Receiver FIFO Table 3a. Receiver FIFO Table 4. Transmitter FIFO MR1 Mode Register 1 MR2 Mode Register 2 Page CSR CLOCK SELECT REGISTER T able 5. Table 6. Bit rate generator characteristics for Crystal or Clock = 3.6864MHz CRCommand Register CR COMMAND REGISTER SC28L91 SR Status Register OPCR Output Port Configuration Register SOPRSet the Output Port Bits (OPR) ROPRReset Output Port Bits (OPR) OPR Output Port Register ACR Auxiliary Control Register ACRAuxiliary Control Register Table 7. ACR 6:4 field definition IPCR Input Port change Register ISRInterrupt Status Register ISR Interrupt Status Register IMRInterrupt Mask Register IMR Interrupt Mask Register IVR/GP Interrupt Vector Register (68k mode) or Generalpurpose register (80XXX mode) CTPU and CTPL Counter/Timer Registers CTPU Counter Timer Preset Upper CTPL Counter Timer Preset Low Output Port Notes The CTS, RTS, CTS Enable Tx signals 2004 Oct 21 33 SD00696 80XXX Mode 68XXX Mode Figure 4. Reset Timing SD00087 2004 Oct 21 34 Figure 6. Bus Timing (Read Cycle) (68XXX mode) 2004 Oct 21 35 Figure 8. Interrupt Cycle Timing (68XXX mode) Figure 9. Port Timing 2004 Oct 21 36 SD00136 Figure 11. Clock Timing SD00704 Figure 10. Interrupt Timing (80xxx mode) 2004 Oct 21 37 SD00138 Figure 14. Transmitter Timing Figure 12. Transmitter External Clocks SD00139 2004 Oct 21 38 SD00156 Figure 16. Wake-Up Mode Figure 15. Receiver Timing SD00096 Page Page Page REVISION HISTOR Y Definitions Disclaimers Contact information Data sheet status