Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 23
MR1 – Mode Register 1
Addr BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MR1 Rx CONTROLS
RTS RxINT
BIT 1 ERROR
MODE PARITY MODE PARITY TYPE BITS PER
CHARACTER
0x00 0 = No
1 = Yes 0 = RxRDY
1 = FFULL 0 = Char
1 = Block 00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multi-drop Mode
0 = Even
1 = Odd 00 = 5
01 = 6
10 = 7
11 = 8
NOTE:
In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR1 is accessed when the MR pointer points to MR1. The pointer is
set to MR1 by RESET or by a ‘set pointer’ command applied via CR
command 0x10. After reading or writing MR1, the pointer will point to
MR2 and will not move from MR2 on subsequent MR reads or
writes.
MR1[7]— Receiver Request–to–Send Control (Flow Control)
This bit controls the deactivation of the RTSN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. Proper automatic operation of flow
control requires OPR[0] to be set to logical 1.
MR1[7] = 1 causes RTSN to be negated (OP0 is driven to a ‘1’
[VCC]) upon receipt of a valid start bit if the FIFO is full. This is the
beginning of the reception of the ninth byte. If the FIFO is not read
before the start of the tenth or 17th byte, an overrun condition will
occur and the tenth or 17th or 17th byte will be lost. However, the bit
in OPR[0] is not reset and RTSN will be asserted again when an
empty FIFO position is available. This feature can be used for flow
control to prevent overrun in the receiver by using the RTSN output
signal to control the CTSN input of the transmitting device.
MR1[6]—Rx Interrupt Bit 1
Bit 1 of the receiver interrupt control. See description under MR0[6].
MR1[5]— Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, and received break) for. In the ‘character’ mode, status is
provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO. In the ‘block’ mode, the
status provided in the SR for these bits is the accumulation
(logical-OR) of the status for all characters coming to the top of the
FIFO since the last ‘reset error’ command was issued.
MR1[4:3|— Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1[4:3] = 11 selects operation in the special
multi–drop mode described in the Operation section.
MR1[2]— Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multi-drop mode it
selects the polarity of the A/D bit.
MR1[1:0]— Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.