Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21 32
CTPU and CTPL – Counter/Timer Registers
CTPU Counter Timer Preset Upper
CTPU Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x06 The lower eight (8) bits for the 16 bit counter timer preset register
CTPL Counter –Timer Preset Low
CTPL Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x07 The Upper eight (8) bits for the 16 bit counter timer preset register
The CTPU and CTPL hold the eight MSbs and eight Labs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which
may be loaded into the CTPU/CTPL registers is H‘0002’. Note that
these registers are write-only and cannot be read by the CPU.
In the timer mode, the C/T generates a square wave whose period is
twice the value (in C/T clock periods) of the CTPU and CTPL. The
waveform so generated is often used for a data clock. The formula
for calculating the divisor n to load to the CTPU and CTPL for a
particular 1X data clock is shown below.
n = (C/T Clock Frequency) divided by (2 x 16 x Baud rate desired)
Often this division will result in a non-integer number; 26.3, for
example. One can only program integer numbers in a digital divider.
Therefore 26 would be chosen. This gives a baud rate error of
0.3/26.3 which is 1.14%; well within the ability asynchronous mode
of operation.
The C/T will not be running until it receives an initial ‘Start Counter’
command (read at address A3–A0 = 1110). After this, while in timer
mode, the C/T will run continuously. Receipt of a start counter
command (read with A3–A0 = 1110) causes the counter to terminate
the current timing cycle and to begin a new cycle using the values in
CTPU and CTPL. If the value in CTPU and CTPL is changed, the
current half-period will not be affected, but subsequent half periods
will be affected.
The counter ready status bit (ISR[3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command (read with
A3–A0 = 0xF). The command however, does not stop the C/T. The
generated square wave is output on OP3 if it is programmed to be
the C/T output. In the counter mode, the value C/T loaded into
CTPU and CTPL by the CPU is counted down to 0. Counting begins
upon receipt of a start counter command. Upon reaching terminal
count 0x0000, the counter ready interrupt bit (ISR[3]) is set. The
counter continues counting past the terminal count until stopped by
the CPU. If OP3 is programmed to be the output of the C/T, the
output remains high until terminal count is reached, at which time it
goes low. The output returns to the High state and ISR[3] is cleared
when the counter is stopped by a stop counter command. The CPU
may change the values of CTPU and CTPL at any time, but the new
count becomes effective only on the next start counter commands. If
new values have not been loaded, the previous count values are
preserved and used for the next count cycle.
In the counter mode, the current value of the upper and lower 8 bits
of the counter (CTU, CTL) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent
potential problems which may occur if a carry from the lower 8 bits
to the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTPU and CTPL.
When the C/T clock divided by 16 is selected, the maximum divisor
becomes 1,048,575.
Output Port Notes
The output ports are controlled from four places: the OPCR register,
the OPR register, the MR registers and the command register
(except the 2681 and 68681) The OPCR register controls the source
of the data for the output ports OP2 through OP7. The data source
for output ports OP0 and OP1 is controlled by the MR and CR
registers. When the OPR is the source of the data for the output
ports, the data at the ports is inverted from that in the OPR register.
The content of the OPR register is controlled by the “Set Output Port
Bits Command” and the “Reset Output Bits Command”. These
commands are at E and F, respectively. When these commands are
used, action takes place only at the bit locations where ones exist.
For example, a one in bit location 5 of the data word used with the
“Set Output Port Bits” command will result in OPR[5] being set to
one. The OP5 would then be set to zero (V SS ). Similarly, a one in
bit position 5 of the data word associated with the “Reset Output
Ports Bits” command would set OPR[5] to zero and, hence, the pin
OP5 to a one (VDD).
The CTS, RTS, CTS Enable Tx signals
CTS (Clear To Send) is usually meant to be a signal to the
transmitter meaning that it may transmit data to the receiver. The
CTS input is on pin IP0 for Tx. The CTS signal is active low; thus, it
is called CTSN for TxRTS is usually meant to be a signal from the
receiver indicating that the receiver is ready to receive data. It is
also active low and is, thus, called RTSN for Rx. RTSN is on pin
OP0. A receiver’s R TS output will usually be connected to the CTS
input of the associated transmitter. Therefore, one could say that
RTS and CTS are different ends of the same wire!
MR2[4] is the bit that allows the transmitter to be controlled by the
CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input
is driven high, the transmitter will stop sending data at the end of the
present character being serialized. It is usually the RTS output of the
receiver that will be connected to the transmitter’s CTS input. The
receiver will set RTS high when the receiver FIFO is full AND the
start bit of the ninth or 17th character is sensed. T ransmission then
stops with nine or 17 valid characters in the receiver. When MR2[4]
is set to one, CTSN must be at zero for the transmitter to operate. If
MR2[4] is set to zero, the IP pin will have no effect on the operation
of the transmitter. MR1[7] is the bit that allows the receiver to control
OP0. When OP0 (or OP1) is controlled by the receiver, the meaning
of that pin will be.