Philips SC28L91 - page 25

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 25

6. The last character will be transmitted and OPR[0] will be reset

one bit time after the last stop bit, causing RTSN to be negated.

MR2[4]— Clear-to-Send Control

If this bit is 0, CTSN has no effect on the transmitter. If this bit is a 1,

the transmitter checks the state of CTSN (IP0) the time it is ready to

send a character. If IP0 is asserted (Low), the character is

transmitted. If it is negated (High), the TxD output remains in the

marking state and the transmission is delayed until CTSN goes low.

Changes in CTSN while a character is being transmitted do not

affect the transmission of that character..

MR2[3:0]— Stop Bit Length Select

This field programs the length of the stop bit appended to the

transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2

bits, in increments of 1/16 bit, can be programmed for character

lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1–1/16

to 2 stop bits can be programmed in increments of 1/16 bit. In all

cases, the receiver only checks for a ‘mark’ condition at the center

of the stop bit position (one half-bit time after the last data bit, or

after the parity bit if enabled is sampled).

If an external 1X clock is used for the transmitter, then MR2[3] = 0

selects one stop bit and MR2[3] = 1 selects two stop bits to be

transmitted.

Contents

Main SC28L91 DESCRIPTION FEATURES Page 2004 Oct 21 4 PIN CONFIGURATION DIAGRAM 80XXX PIN CONFIGURATION Note: Pins marked No Connection must NOT be connected. SD00699 SD00698 3.3 V or 5.0 V Universal Asynchronous 2004 Oct 21 5 PIN CONFIGURATION DIAGRAM 68XXX PIN CONFIGURATION Note: Pins marked No Connection must NOT be connected. SD00701 2004 Oct 21 6 SD00702 Figure 1. Block Diagram (80XXX mode) 2004 Oct 21 7 SD00703 Figure 2. Block Diagram (68XXX mode) SC28L91 PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL) SC28L91 PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA) ABSOLUTE MAXIMUM RA TINGS DC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS (5 VOL T) Page AC CHARACTERISTICS (3.3 VOL T) Page Block Diagram Data Bus Buffer Operation Control Interrupt Control TIMING CIRCUITS Crystal Clock BRG Counter/Timer Timer Mode Counter Mode Timeout Mode Time Out Mode Caution Communications Input Port Output Port OPERATION Transmitter Receiver Transmitter Reset and Disable Receiver FIFO Receiver Status Bits Receiver Reset and Disable Watchdog Receiver Time-out Mode Watchdog and Time Out Mode Differences Multi-drop Mode (9-bit or Wake-Up) PROGRAMMING Table 1. SC28L91 register addressing Table 2. Condensed Register bit formats REGISTER DESCRIPTIONS MODE REGISTERS MR0 Mode Register 0 Table 3. Receiver FIFO Table 3a. Receiver FIFO Table 4. Transmitter FIFO MR1 Mode Register 1 MR2 Mode Register 2 Page CSR CLOCK SELECT REGISTER T able 5. Table 6. Bit rate generator characteristics for Crystal or Clock = 3.6864MHz CRCommand Register CR COMMAND REGISTER SC28L91 SR Status Register OPCR Output Port Configuration Register SOPRSet the Output Port Bits (OPR) ROPRReset Output Port Bits (OPR) OPR Output Port Register ACR Auxiliary Control Register ACRAuxiliary Control Register Table 7. ACR 6:4 field definition IPCR Input Port change Register ISRInterrupt Status Register ISR Interrupt Status Register IMRInterrupt Mask Register IMR Interrupt Mask Register IVR/GP Interrupt Vector Register (68k mode) or Generalpurpose register (80XXX mode) CTPU and CTPL Counter/Timer Registers CTPU Counter Timer Preset Upper CTPL Counter Timer Preset Low Output Port Notes The CTS, RTS, CTS Enable Tx signals 2004 Oct 21 33 SD00696 80XXX Mode 68XXX Mode Figure 4. Reset Timing SD00087 2004 Oct 21 34 Figure 6. Bus Timing (Read Cycle) (68XXX mode) 2004 Oct 21 35 Figure 8. Interrupt Cycle Timing (68XXX mode) Figure 9. Port Timing 2004 Oct 21 36 SD00136 Figure 11. Clock Timing SD00704 Figure 10. Interrupt Timing (80xxx mode) 2004 Oct 21 37 SD00138 Figure 14. Transmitter Timing Figure 12. Transmitter External Clocks SD00139 2004 Oct 21 38 SD00156 Figure 16. Wake-Up Mode Figure 15. Receiver Timing SD00096 Page Page Page REVISION HISTOR Y Definitions Disclaimers Contact information Data sheet status