Philips SC28L91 SC28L91

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 8

PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL)

Symbol Pin

type Name and function

I/M IBus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table.

D0–D7 I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the

CPU. D0 is the least significant bit.

CEN IChip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on

D0–D7 as controlled by the WRN, RDN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condi-

tion.

WRN IWrite Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register . The

transfer occurs on the rising edge of the signal.

RDN IRead Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the

data bus. The read cycle begins on the falling edge of RDN.

A0–A3 IAddress Inputs: Select the UART internal registers and ports for read/write operations.

RESET IReset: A High level clears internal registers (SR, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state, stops the

counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets MR point-

er to MR1. See Figure 4

INTRN OInterrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable in-

terrupting conditions are true. This pin requires a pull-up device.

X1/CLK ICrystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a

crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

X2 OCrystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin

to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

RxD IReceiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.

TxD OTransmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark” condition

when the transmitter is disabled, idle or operating in local loop back mode. “Mark” is High; “space” is Low.

OP0 OOutput 0: General-purpose output or request to send (RTSN, active-Low). Can be deactivated automatically on re-

ceive or transmit.

OP1 OOutput 1: General-purpose output.

OP2 OOutput 2: General-purpose output, or transmitter 1X or 16X clock output, or receiver 1X clock output.

OP3 OOutput 3: General-purpose output.

OP4 OOutput 4: General-purpose output or open-drain, active-Low, Rx interrupt ISR[1] output. DMA Control

OP5 OOutput 5: General-purpose output

OP6 OOutput 6: General-purpose output or open-drain, active-Low, Tx interrupt ISR[0] output. DMA Control

OP7 OOutput 7: General-purpose output.

IP0 IInput 0: General-purpose input or clear to send active-Low input (CTSN). Has Change of State Dector.

IP1 IInput 1: General-purpose input. Has Change of State Dector.

IP2 I Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.

IP3 IInput 3: General-purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

IP4 IInput 4: General-purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

the received data is sampled on the rising edge of the clock.

IP5 IInput 5: General-purpose input

IP6 IInput 6: General-purpose input

VCC Pwr Power Supply: +3.3 V or +5 V supply input ± 10 %

GND Pwr Ground

Contents

Main SC28L91 DESCRIPTION FEATURES Page 2004 Oct 21 4 PIN CONFIGURATION DIAGRAM 80XXX PIN CONFIGURATION Note: Pins marked No Connection must NOT be connected. SD00699 SD00698 3.3 V or 5.0 V Universal Asynchronous 2004 Oct 21 5 PIN CONFIGURATION DIAGRAM 68XXX PIN CONFIGURATION Note: Pins marked No Connection must NOT be connected. SD00701 2004 Oct 21 6 SD00702 Figure 1. Block Diagram (80XXX mode) 2004 Oct 21 7 SD00703 Figure 2. Block Diagram (68XXX mode) SC28L91 PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL) SC28L91 PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA) ABSOLUTE MAXIMUM RA TINGS DC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS (5 VOL T) Page AC CHARACTERISTICS (3.3 VOL T) Page Block Diagram Data Bus Buffer Operation Control Interrupt Control TIMING CIRCUITS Crystal Clock BRG Counter/Timer Timer Mode Counter Mode Timeout Mode Time Out Mode Caution Communications Input Port Output Port OPERATION Transmitter Receiver Transmitter Reset and Disable Receiver FIFO Receiver Status Bits Receiver Reset and Disable Watchdog Receiver Time-out Mode Watchdog and Time Out Mode Differences Multi-drop Mode (9-bit or Wake-Up) PROGRAMMING Table 1. SC28L91 register addressing Table 2. Condensed Register bit formats REGISTER DESCRIPTIONS MODE REGISTERS MR0 Mode Register 0 Table 3. Receiver FIFO Table 3a. Receiver FIFO Table 4. Transmitter FIFO MR1 Mode Register 1 MR2 Mode Register 2 Page CSR CLOCK SELECT REGISTER T able 5. Table 6. Bit rate generator characteristics for Crystal or Clock = 3.6864MHz CRCommand Register CR COMMAND REGISTER SC28L91 SR Status Register OPCR Output Port Configuration Register SOPRSet the Output Port Bits (OPR) ROPRReset Output Port Bits (OPR) OPR Output Port Register ACR Auxiliary Control Register ACRAuxiliary Control Register Table 7. ACR 6:4 field definition IPCR Input Port change Register ISRInterrupt Status Register ISR Interrupt Status Register IMRInterrupt Mask Register IMR Interrupt Mask Register IVR/GP Interrupt Vector Register (68k mode) or Generalpurpose register (80XXX mode) CTPU and CTPL Counter/Timer Registers CTPU Counter Timer Preset Upper CTPL Counter Timer Preset Low Output Port Notes The CTS, RTS, CTS Enable Tx signals 2004 Oct 21 33 SD00696 80XXX Mode 68XXX Mode Figure 4. Reset Timing SD00087 2004 Oct 21 34 Figure 6. Bus Timing (Read Cycle) (68XXX mode) 2004 Oct 21 35 Figure 8. Interrupt Cycle Timing (68XXX mode) Figure 9. Port Timing 2004 Oct 21 36 SD00136 Figure 11. Clock Timing SD00704 Figure 10. Interrupt Timing (80xxx mode) 2004 Oct 21 37 SD00138 Figure 14. Transmitter Timing Figure 12. Transmitter External Clocks SD00139 2004 Oct 21 38 SD00156 Figure 16. Wake-Up Mode Figure 15. Receiver Timing SD00096 Page Page Page REVISION HISTOR Y Definitions Disclaimers Contact information Data sheet status