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Philips SC28L91 Table 2. Condensed Register bit formats

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Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21 21

Register Acronyms and Read / Write Capability

(R/W = Read/Write, R = Read only, W = Write only)

Mode Register MRn R/W

Status Register SR R

Clock Select CSR W

Command Register CR W

Receiver FIFO RxFIFO R

T ransmitter FIFO RxFIFO W

Input Port Change Register IPCR R

Auxiliary Control Register ACR W

Interrupt Status Register ISR R

Interrupt Mask Register IMR W

Counter T imer Upper Value CTU R

Counter T imer Lower Value CTL R

Counter T imer Preset Upper CTPU W

Counter T imer Preset Lower CTPL W

Input Port Register IPR R

Output Configuration Register OPCR W

Set Output Port Bits W

Reset Output Port Bits W

Interrupt vector or GP register IVR/GP R/W

Table 2. Condensed Register bit formats

Name Adr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MR0 0WATCH

DOG RxINT BIT 2 TxINT [1:0] FIFO SIZE BAUD RATE

EXTENDED

II

TEST 2 BAUD RATE

EXTENDED 1

MR1 0RxRTS

Control RxINT BIT 1 Error Mode Parity Mode Parity Type Bits per Character

MR2 0Channel Mode TxRTS

Control CTSN Enable

Tx Stop Bit Length

CSR 1Receiver Clock, Select Code T ransmitter Clock select code,

SR 1Received

Break Framing

Error Parity Error Overrun Error TxEMT TxRDY RxFULL RxRDY

CR 2Channel Command codes Disable Tx Enable Tx Disable Rx Enable Rx

RxFIFO 3Read 8 bits from Rx FIFO

TxFIFO 3Write 8 bits to Tx FIFO

IPCR 4Delta IP3 Delta IP2 Delta IP1 Delta IP0 State of IP3 State of IP2 State of IP1 State of IP0

ACR 4Baud Group Counter Timer mode and clock select Enable IP3 Enable IP2 Enable IP1 Enable IP0

ISR 5Change

Input Port Ignore in ISR Reads Counter

Ready Change

Break RxRDY TxRDY

IMR 5Change

Input Port Set to 0 Set to 0 Set to 0 Counter

Ready Change

Break RxRDY TxRDY

CTU 6Read 8 MSb of the BRG T imer divisor.

CTPU 6Write 8 MSb of the BRG Timer divisor.

CTL 7Read 8 LSb of the BRG T imer divisor.

CTPL 7Write 8 LSb of the BRG Timer divisor.

IPR DState of IP State of IP 6 State of IP 5 State of IP 4 State of IP 3 State of IP 2 State of IP1 State of IP 0

OPCR DConfigure

OP7 Configure

OP6 Configure

OP5 Configure

OP4 Configure OP3 Configure OP2

Strt C/T ERead Address E to start Counter T imer

SOPR ESet OP 7 Set OP 6 Set OP 5 Set OP 4 Set OP 3 Set OP 2 Set OP 1 Set OP 0

Stp C/T FRead Address F to stop counter T imer

ROPR FReset OP 7 Reset OP 6 Reset OP 5 Reset OP 4 Reset OP 3 Reset OP 2 Reset OP 1 Reset OP 0

Contents

Main SC28L91 DESCRIPTION FEATURES Page 2004 Oct 21 4 PIN CONFIGURATION DIAGRAM 80XXX PIN CONFIGURATION Note: Pins marked No Connection must NOT be connected. SD00699 SD00698 3.3 V or 5.0 V Universal Asynchronous 2004 Oct 21 5 PIN CONFIGURATION DIAGRAM 68XXX PIN CONFIGURATION Note: Pins marked No Connection must NOT be connected. SD00701 2004 Oct 21 6 SD00702 Figure 1. Block Diagram (80XXX mode) 2004 Oct 21 7 SD00703 Figure 2. Block Diagram (68XXX mode) SC28L91 PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL) SC28L91 PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA) ABSOLUTE MAXIMUM RA TINGS DC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS (5 VOL T) Page AC CHARACTERISTICS (3.3 VOL T) Page Block Diagram Data Bus Buffer Operation Control Interrupt Control TIMING CIRCUITS Crystal Clock BRG Counter/Timer Timer Mode Counter Mode Timeout Mode Time Out Mode Caution Communications Input Port Output Port OPERATION Transmitter Receiver Transmitter Reset and Disable Receiver FIFO Receiver Status Bits Receiver Reset and Disable Watchdog Receiver Time-out Mode Watchdog and Time Out Mode Differences Multi-drop Mode (9-bit or Wake-Up) PROGRAMMING Table 1. SC28L91 register addressing Table 2. Condensed Register bit formats REGISTER DESCRIPTIONS MODE REGISTERS MR0 Mode Register 0 Table 3. Receiver FIFO Table 3a. Receiver FIFO Table 4. Transmitter FIFO MR1 Mode Register 1 MR2 Mode Register 2 Page CSR CLOCK SELECT REGISTER T able 5. Table 6. Bit rate generator characteristics for Crystal or Clock = 3.6864MHz CRCommand Register CR COMMAND REGISTER SC28L91 SR Status Register OPCR Output Port Configuration Register SOPRSet the Output Port Bits (OPR) ROPRReset Output Port Bits (OPR) OPR Output Port Register ACR Auxiliary Control Register ACRAuxiliary Control Register Table 7. ACR 6:4 field definition IPCR Input Port change Register ISRInterrupt Status Register ISR Interrupt Status Register IMRInterrupt Mask Register IMR Interrupt Mask Register IVR/GP Interrupt Vector Register (68k mode) or Generalpurpose register (80XXX mode) CTPU and CTPL Counter/Timer Registers CTPU Counter Timer Preset Upper CTPL Counter Timer Preset Low Output Port Notes The CTS, RTS, CTS Enable Tx signals 2004 Oct 21 33 SD00696 80XXX Mode 68XXX Mode Figure 4. Reset Timing SD00087 2004 Oct 21 34 Figure 6. Bus Timing (Read Cycle) (68XXX mode) 2004 Oct 21 35 Figure 8. Interrupt Cycle Timing (68XXX mode) Figure 9. Port Timing 2004 Oct 21 36 SD00136 Figure 11. Clock Timing SD00704 Figure 10. Interrupt Timing (80xxx mode) 2004 Oct 21 37 SD00138 Figure 14. Transmitter Timing Figure 12. Transmitter External Clocks SD00139 2004 Oct 21 38 SD00156 Figure 16. Wake-Up Mode Figure 15. Receiver Timing SD00096 Page Page Page REVISION HISTOR Y Definitions Disclaimers Contact information Data sheet status