Philips TDA5051A - page 11

1999 May 31 11

Philips Semiconductors Product speciﬁcation

Home automation modem TDA5051A

Table 1 Clock oscillator parameters

Table 2 Calculation of parameters depending on the clock frequency

OSCILLATOR

FREQUENCY

fosc

CARRIER FREQUENCY

fcr

CLOCK OUTPUT

FREQUENCY

1⁄2fosc

EXTERNAL COMPONENTS

6.080 to 9.504 MHz 95 to 148.5 kHz 3.040 to 4.752 MHz C1 = C2 = 27 to 47 pF;

Rp= 2.2 to 4.7 MΩ;

XTAL= standard quartz crystal

SYMBOL PARAMETER CONDITIONS UNIT

fosc oscillator frequency with on-chip oscillator: frequency of the crystal

quartz; with external clock: frequency of the

signal applied at OSC1

Hz

fCLKOUT clock output frequency 1⁄2fosc Hz

fcr carrier frequency/digital ﬁlter tuning

frequency

1⁄64fosc Hz

tsu set-up time of the shaped burst or s

thhold time of the shaped burst or s

tW(DI)(min) minimum pulse width of DATAIN signal tsu +s

tW(burst)(min) minimum burst time of VO(DC) signal tW(DI)(min) +t

hs

t

c(AGC) AGC time constant s

tsu(demod) demodulation set-up time (≈max.) s

th(demod) demodulation hold time (≈max.) s

23

fcr

------ 1472

fosc

-------------

23

fcr

------ 1472

fosc

-------------

1

fcr

-----

2514

fosc

-------------

3200

fosc

-------------

3800

fosc

-------------

Contents

Main Page 1999 May 31 3 ORDERING INFORMATION Fig.1 Block diagram. BLOCK DIAGRAM Page Home automation modem TDA5051A Page Page Page 1999 May 31 9 Fig.4 Shaped signal spectrum. Fig.5 AGC time constant definition (not to scale). 1999 May 31 10 TIMING Conguration for clock TDA5051A Fig.7 Typical configuration for on-chip clock circuit. Fig.6 External clock. Page Page 1999 May 31 13 Timing diagrams Fig.11 Timing diagram during power-up in reception mode. Fig.10 Timing diagram during power-up in transmission mode. 1999 May 31 14 Fig.12 Power-down sequence in transmission mode. Fig.14 Power saving by dynamic control of power-down. Fig.13 Power-down sequence in reception mode. 1999 May 31 15 TEST INFORMATION Fig.15 Test set-up for measuring demodulation delay. 1999 May 31 16 Fig.16 Test set-up for measuring THD and bandwidth of the TXOUT signal. 1999 May 31 17 TDA5051A Fig.17 Test set-up for measuring Bit Error Rate (BER). 1999 May 31 18 APPLICATION INFORMATION Fig.18 Application diagram without power line insulation. 1999 May 31 19 1999 May 31 20 Fig.21 Application diagram with power line insulation. 1999 May 31 21 Fig.22 Application diagram without power line insulation, with improved sensitivity (68 dBV typ.). 1999 May 31 22 Fig.23 Application diagram with power line insulation, with improved sensitivity (68 dBV typ.). 1999 May 31 23 PACKAGE OUTLINE SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 Data Handbook IC26; Integrated Circuit Packages Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods Page Page Philips Semiconductors a worldwide company Printed in The Netherlands