Philips TDA5051A - page 7

1999 May 31 7

Philips Semiconductors Product speciﬁcation

Home automation modem TDA5051A

tW(DI)(min) minimum pulse width of

DATAIN signal fosc = 8.48 MHz;

see Fig.8

−190 −µs

V

o(rms) output carrier signal

(RMS value) ZL= CISPR16;

DATAIN= LOW 120 −122 dBµV

Io(max) power ampliﬁer maximum

output current (peak value) ZL=1Ω;

DATAIN= LOW

−160 −mA

Zooutput impedance of the

power ampliﬁer

−5−Ω

V

Ooutput DC level at

pin TXOUT

−2.5 −V

THD total harmonic distortion on

CISPR16 load with the

coupling network

(measured on the ﬁrst ten

harmonics)

Vo(rms) = 121 dBµV on

CISPR16 load;

fosc = 8.48 MHz;

DATAIN= LOW

(no modulation);

see Figs 3 and 16

−−55 −dB

B−20dB bandwidth of the shaped

output signal (at −20 dB)

on CISPR16 load with the

coupling network

Vo(rms) = 121 dBµV on

CISPR16 load;

fosc = 8.48 MHz;

DATAIN= 300 Hz;

duty factor = 50%;

see Fig.4

−3000 −Hz

Reception mode

Vi(rms) analog input signal

(RMS value) 82 −122 dBµV

VIDC level at pin RXIN −2.5 −V

ZiRXIN input impedance −50 −kΩ

RAGC AGC range −36 −dB

tc(AGC) AGC time constant fosc = 8.48 MHz;

see Fig.5

−296 −µs

t

d(dem)(su) demodulation delay set-up

time fosc = 8.48 MHz;

see Fig.15

−350 400 µs

td(dem)(h) demodulation delay hold

time fosc = 8.48 MHz;

see Fig.15

−420 470 µs

Bdet detection bandwidth fosc = 8.48 MHz −3−kHz

BER bit error rate fosc = 8.48 MHz;

600 baud; S/N = 35 dB;

signal 76 dBµV;

see Fig.17

−1−1×10−4

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Contents

Main Page 1999 May 31 3 ORDERING INFORMATION Fig.1 Block diagram. BLOCK DIAGRAM Page Home automation modem TDA5051A Page Page Page 1999 May 31 9 Fig.4 Shaped signal spectrum. Fig.5 AGC time constant definition (not to scale). 1999 May 31 10 TIMING Conguration for clock TDA5051A Fig.7 Typical configuration for on-chip clock circuit. Fig.6 External clock. Page Page 1999 May 31 13 Timing diagrams Fig.11 Timing diagram during power-up in reception mode. Fig.10 Timing diagram during power-up in transmission mode. 1999 May 31 14 Fig.12 Power-down sequence in transmission mode. Fig.14 Power saving by dynamic control of power-down. Fig.13 Power-down sequence in reception mode. 1999 May 31 15 TEST INFORMATION Fig.15 Test set-up for measuring demodulation delay. 1999 May 31 16 Fig.16 Test set-up for measuring THD and bandwidth of the TXOUT signal. 1999 May 31 17 TDA5051A Fig.17 Test set-up for measuring Bit Error Rate (BER). 1999 May 31 18 APPLICATION INFORMATION Fig.18 Application diagram without power line insulation. 1999 May 31 19 1999 May 31 20 Fig.21 Application diagram with power line insulation. 1999 May 31 21 Fig.22 Application diagram without power line insulation, with improved sensitivity (68 dBV typ.). 1999 May 31 22 Fig.23 Application diagram with power line insulation, with improved sensitivity (68 dBV typ.). 1999 May 31 23 PACKAGE OUTLINE SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 Data Handbook IC26; Integrated Circuit Packages Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods Page Page Philips Semiconductors a worldwide company Printed in The Netherlands