Philips TDA5051A - page 8

1999 May 31 8

Philips Semiconductors Product speciﬁcation

Home automation modem TDA5051A

Power-up timing

td(pu)(TX) delay between power-up

and DATAIN in

transmission mode

XTAL= 8.48 MHz;

C1 = C2 = 27 pF;

Rp= 2.2 MΩ; see Fig.10

−1−µs

t

d(pu)(RX) delay between power-up

and DATAOUT in reception

mode

XTAL= 8.48 MHz;

C1 = C2 = 27 pF;

Rp= 2.2 MΩ;

fRXIN = 132.5 kHz;

120 dBµV sine wave;

see Fig.11

−1−µs

Power-down timing

td(pd)(TX) delay between PD = 0 and

DATAIN in transmission

mode

fosc = 8.48 MHz;

see Fig.12

−10 −µs

t

d(pd)(RX) delay between PD = 0 and

DATAOUT in reception

mode

fosc = 8.48 MHz;

fRXIN = 132.5 kHz;

120 dBµV sine wave;

see Fig.13

−500 −µs

t

active(min) minimum active time with

T = 10 ms power-down

period in reception mode

fosc = 8.48 MHz;

fRXIN = 132.5 kHz;

120 dBµV sine wave;

see Fig.14

−1−µs

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Fig.3 Carrier spectrum.

Resolution bandwidth= 9 kHz; top: 0 dBV (RMS) = 120 dBµV (RMS); marker at −5 dBV (RMS) = 115 dBµV (RMS);

the CISPR16 network provides an attenuation of 6dB, so the signal amplitude is 121 dBµV (RMS).

d

book, full pagewidth

−100

0

MGK834

132.5 kHz

Vo(rms)

(dBV)

106

105f (Hz)

Contents

Main Page 1999 May 31 3 ORDERING INFORMATION Fig.1 Block diagram. BLOCK DIAGRAM Page Home automation modem TDA5051A Page Page Page 1999 May 31 9 Fig.4 Shaped signal spectrum. Fig.5 AGC time constant definition (not to scale). 1999 May 31 10 TIMING Conguration for clock TDA5051A Fig.7 Typical configuration for on-chip clock circuit. Fig.6 External clock. Page Page 1999 May 31 13 Timing diagrams Fig.11 Timing diagram during power-up in reception mode. Fig.10 Timing diagram during power-up in transmission mode. 1999 May 31 14 Fig.12 Power-down sequence in transmission mode. Fig.14 Power saving by dynamic control of power-down. Fig.13 Power-down sequence in reception mode. 1999 May 31 15 TEST INFORMATION Fig.15 Test set-up for measuring demodulation delay. 1999 May 31 16 Fig.16 Test set-up for measuring THD and bandwidth of the TXOUT signal. 1999 May 31 17 TDA5051A Fig.17 Test set-up for measuring Bit Error Rate (BER). 1999 May 31 18 APPLICATION INFORMATION Fig.18 Application diagram without power line insulation. 1999 May 31 19 1999 May 31 20 Fig.21 Application diagram with power line insulation. 1999 May 31 21 Fig.22 Application diagram without power line insulation, with improved sensitivity (68 dBV typ.). 1999 May 31 22 Fig.23 Application diagram with power line insulation, with improved sensitivity (68 dBV typ.). 1999 May 31 23 PACKAGE OUTLINE SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 Data Handbook IC26; Integrated Circuit Packages Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods Page Page Philips Semiconductors a worldwide company Printed in The Netherlands