Philips TDA8783 40 Msps, 10-bit analog-to-digital

2002 Oct 23 10

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

interface for CCD cameras TDA8783

Clamps

gm(ADC) ADC clamp transconductance at clamp level −7−mS

gm(CDS) CDS clamp transconductance at clamp level −1.5 −mS

Analog-to-Digital Converter (ADC)

fCLK(max) maximum clock frequency 40 −−MHz

tCPH clock pulse width HIGH 12 −−ns

tCPL clock pulse width LOW 12 −−ns

SRCLK clock input slew rate (risingand

falling edge) 10% to 90% 0.5 −−V/ns

Vi(ADC)(p-p) ADC input voltage level

(peak-to-peak value)

−2−V

VRB ADC reference voltage output

code 0

−1.5 −V

VRT ADC reference voltage output

code 1023

−3.5 −V

IADCIN ADC input current −2−+120 µA

INL integral non-linearity ramp input −±0.6 ±1.5 LSB

DNL differential non-linearity ramp input −±0.2 ±0.75 LSB

td(s) sampling delay time −−5ns

Total chain characteristics(CDS + AGC+ ADC)

tddelay between SHDand CLK 50% at rising edges

CLK and SHD: transition full

scale code 0to 1023;

fcut(CDS) = 120 MHz;

fcut(AGC)= 54 MHz;

Vi(CDS) = 600 mV

−30 −ns

Ntot(rms) total output noise (RMS value) fcut(CDS)= 120 MHz;

fcut(AGC)= 40 MHz; note2

GAGC= 4.5 dB −0.125 −LSB

GAGC = 34.5 dB −1.6 −LSB

Voffset(ﬂ-d) maximum offset between CCD

ﬂoating level and CCD dark pixel

level

−200 −+200 mV

Vn(i)(eq)(rms) equivalent input noise voltage

(RMS value) AGC gain= 34.5dB −125 −µV

AGC gain= 4.5 dB −150 −µV

Digital-to-Analog Converter (OFDOUT)

VOFDOUT(p-p) additional 8-bit control DAC

(OFD) output voltage

(peak-to-peak value)

−1.4 −V

VOFDOUT(0) DC output voltage for code0 −2.3 −V

VOFDOUT(255) DC output voltage for code255 −3.7 −V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT