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| Block | No. | Pin Name | I/O |
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| 7 | LRCLOCK | I | LR clock for audio data input |
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| 8 | SCLOCK | I | Bit clock for audio data input |
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| Audio IN |
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| 3 | SDI0 | I | Audio data serial input (L, R) |
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| 4 | SDI1 | I | Audio data serial input (Ls, Rs) |
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| 5 | SDI2 | I | Audio data serial input (C, LFE) |
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| Audio OUT | 2 | SDO | O | Audio data serial output (L, R) |
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| 41 | ENABLE | I | Command enable input |
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| Host I/F | 40 | CLOCK | I | Serial data input clock |
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| 39 | DATA | I | Address and data input |
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| Reset | 47 | RESET | I | System reset input (Low: reset on) |
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| 14 | R | I | VCO bias resistor pin |
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| PLL | 15 | VCNT | I | VCO control input pin |
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| 23 | MCLOCK | I | Moving clock input pin |
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| 16 | PDO | O | Output pin for VCO charge pump |
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| 1,19 | VDD1 | − | I/O power supply |
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| 25,37,43 | VDD2 | − | Digital power supply |
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| Power | 13 | AVDD | − | Power supply for PLL |
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| supply | 6,20 | VSS1 | − | I/O GND |
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| 31,36,46 | VSS2 | − | Digital GND |
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| 12 | AVSS | − | GND for PLL |
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| Test | 9,10,11,17,24 |
| I | Test pin |
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| 32,38 |
| O | Test pin |
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| 42 | CMODE | I | Parallel (High) / Serial (Low) selection pin |
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| 30 | PRG4 | I |
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| 29 | PRG3 | I |
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| Dolby headphone mode selection pin |
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| 28 | PRG2 | I |
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| 27 | PRG1 | I |
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| 26 | PRG0 | I |
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| Parallel |
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| 35 | FMT2 | I |
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| Audio I/O selection pin |
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| 34 | FMT1 | I |
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| 33 | FMT0 | I |
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| 44 | MUTE | I | Mute pin (High: Mute on) |
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| 45 | STEREO | I | Bypass setting pin of LR signal (High: Stereo bypass) |
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| 18 | PLL STOP | I | Power save pin (Low: PLL circuit OFF) |
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| 21 | PLL1 | I | PLL clock selection pin |
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| 22 | PLL0 | I |
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A
B
C
D
E
F
5 | 6 |
41
7 | 8 |