Chapter 4 Award BIOS Setup
Descriptions on each item are as follows:
1.CPU to PCI Write Buffer
When this field is Enabled, writes from the CPU to the PCI bus are buffered, to compensate for the speed differences between the CPU and the PCI bus. When Disabled, the writes are not buffered and the CPU must wait until the write is complete before starting another write cycle.
2.PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait states.
3.PCI Delay Transaction
The chipset has an embedded
MEMORY HOLE:
In order to improve performance, certain space in memory is reserved for ISA cards. This memory must be mapped into the memory space below 16MB.
SYSTEM BIOS CACHEABLE:
Selecting Enabled allows caching of the system BIOS ROM at F0000h- FFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result.
VIDEO RAM CACHEABLE:
Selecting Enabled allows caching of the video BIOS ROM at C0000h to C7FFFh, resulting in better video performance. However, if any program writes to this memory area, a system error may result.
IO CHANNEL CHECK NMI:
This field allows you to enable or disable IO channel check NMI. Before selecting this function, the user should check first that NMI function is enabled as described in chapter 2 (Reset/NMI/Clear Watchdog Selection).
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