Renesas EDK3687 Preface , Cautions, Trademarks, Document Information

Preface

Cautions

1. This document may be, wholly or partially, subject to change without notice.

document without Renesas Technology Europe Limited's written permission.

Trademarks

General

All brand or product names used in this manual are trademarks or registered trademarks of their respective

companies or organisations.

Specific

Microsoft, MS and MS-DOS are registered trademarks and Windows and Windows NT are

trademarks of Microsoft Corporation.

Document Information

Product Code: D004173_11

Version: 2.0

Date: 09/05/2003

Website: http://www.renesas.com/

Contents

Main Preface Cautions Trademarks Document Information 1. TABLE OF CONTENTS 2. START-UP INSTRUCTIONS 2.1. INSTALLING THE EVALUATION DEVELOPMENT KIT (EDK) 2.2. SERIAL CONNECTION HOST PC EDK 2.3. POWER SUPPLY 3. EDK BOARD LAYOU T Microprocessor J2 The diagram shows a general layout of the EDK board. CJ4 4. EDK OPERATION 4.1. USER INTERFACE 4.2. SERIAL INTERFACE 4.2.1. CONNECTOR PIN DEFINITIONS 4.2.2. CRYSTAL CHOICE 4.2.3. REMOVABLE COMPONENT INFORMATION. 4.3. SPI EEPROM 4.4. I2C EEPROM 4.5. LIN INTERFACE 4.6. LED 5. BOARD OPTIONS 5.1. JUMPER LINKS FIGURE 5-1: JUMPER CONFIGURATION The following tables define each jumper and its settings. 5.2. EDK OPTIONS CJ4 *See section 5.4 The following table lists the connections to each jumper pin. 5.3. OPTION LINK SELECTION 5.3.1. RST RESET FUNCTION 5.3.2. LIN LIN INTERFACE 5.3.3. SPI SERIAL PERIPHERAL INTERFACE 5.3.4. CAN CONTROLLER AREA NETWORK 5.4. FLASH PROGRAMMING HEADER 5.5. EXTERNAL DEBUG HEADER 5.6. BOOT CONTROL 6. MICROCONTROLLER HEADER CONNECTIONS The following table lists the connections to each or the headers on the board. 6.1. H 6.2. H 7. CODE DEVELOPMENT 7.1. HMON 7.1.1. M 7.1.2. BREAKPOINT SUPPORT 7.1.2.1.CODE LOCATED IN FLASH / ROM 7.1.2.2.CODE LOCATED IN RAM 7.1.4. MEMORY MAP 7.1.5. BAUD RATE SETTING 7.1.6. INTERRUPT MASK SECTIONS 7.2. ADDITIONAL INFORMATION