18
11. MFI
When the MFI boot mode is used, be sure to activate the emulator by setting the MFIINT
signal as a trigger for the MFI transfer from the base-band side.
12. Memory Access during Break
In the enabled MMU, when a memory is accessed and a TLB error occurs during break, it can
be selected whether the TLB exception is controlled or the program jumps to the user
exception handler in [TLB Mode] in the [Configuration] dialog box. When [TLB miss
exception is enable] is selected, a “Communication Timeout error” will occur if the TLB
exception handler does not operate correctly. When [TLB miss exception is disable] is selected,
the program does not jump to the TLB exception handler even if a TLB exception occurs.
Therefore, if the TLB exception handler does not operate correctly, a “Communication
Timeout error” will not occur but the memory contents may not be correctly displayed.
13. Loading Sessions
Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading
sessions. Thus the TCK value will be 1.25 MHz.
14. [IO] Window
• Display and modification
Do not change values of the User Break Controller because it is used by the emulator.
For each RCLK watchdog timer register, there are two registers to be separately used for
write and read operations.
Table 2.3 RCLK Watchdog Timer Register
Register Name Usage Register
RWTCSR(W) Write RCLK watchdog timer control/status register
RWTCNT(W) Write RCLK watchdog timer counter
RWTCSR(R) Read RCLK watchdog timer control/status register
RWTCNT(R) Read RCLK watchdog timer counter