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Notes: 1. The memory range for which trace is output is the address on the system bus and not
supported for the MMU or cache.
2. In the memory range for output, do not specify the ranges that the user program has
been downloaded or the user program accesses.
3. Do not select an internal RAM area as the memory range for output.
4. The range for trace output must be 1 MB or less.
2.2.3 Notes on Using the JTAG (H-UDI) Clock (TCK) and AUD Clock (AUDCK)
1. Set the JTAG clock (TCK) frequency to lower than the frequency of the SH7362 peripheral
module clock (CKP).
2. Set the AUD clock (AUDCK) frequ ency to 50 MHz or lower. If the frequency is higher than
50 MHz, the emulator will not operate normally.
3. The set v alue of the JTAG clock (TCK) is initialized by executing [Reset CPU] or [Reset Go].
Thus the TCK value will be 1.25 MHz. When the [Search the best JTAG clock] option has
been selected at initiation of the emulator, the TCK value is initialized to a value that was
automatically acquired.
2.2.4 Notes on Setting the [Breakpoint] Dialog Box
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.
Accordingly, it can be set only to the RAM areas in CS0 to CS6 and the internal RAM areas.
A BREAKPOINT cannot be set to the following addresses:
ROM areas in CS0 to CS6
Areas other than CS0 to CS6 except for the internal RAM
A slot instruction of a delayed branch instruction
An area that can be only read by MMU
3. During step operation, BREAKPOINTs are disabled.
4. When execution resumes from the address where a BREAKPOINT is specified, single-step
operation is performed at the address before execution resumes. Therefore, realtime operation
cannot be performed.
5. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
6. Note on DSP repeat loop:
A BREAKPOINT is equal to a branch instruction. In some DSP repeat loops, branch