3.IC902, IC904, IC908 (H Driver) and IC907 (V Driver)

An H driver and V driver are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD.

IC902, IC904 and IC908 are inverter IC which drives the hori- zontal CCDs (H1 and H2). In addition the XV1-XV3 signals which are output from IC102 are the vertical transfer clocks, and the XSG1 and XSG signal which is output from IC102 is superimposed onto XV2A and XV2B at IC907 in order to gen- erate a ternary pulse. In addition, the XSUB signal which is output from IC102 is used as the sweep pulse for the elec- tronic shutter, and the RG signal which is output from IC102 is the reset gate clock.

1A

1

14

VCC

1Y

2

13

6A

2A

3

12

6Y

2Y

4

11

5A

3A

5

10

5Y

3Y

6

9

4A

GND 7

8

4Y

Fig. 1-3. IC902, IC904 and IC908 Block Diagram

4.IC905 (CDS, AGC Circuit and A/D Converter)

The video signal which is output from the CCD is input to Pin (30) of IC905. There are S/H blocks inside IC905 generated from the XSHP and XSHD pulses, and it is here that CDS (correlated double sampling) is carried out.

After passing through the CDS circuit, the signal passes through the AGC amplifier. It is A/C converted internally into a 10-bit signal, and is then input to IC102 of the CA2 circuit board. The gain of the AGC amplifier is controlled by serial data which is output from IC102 of the CA2 circuit board.

PBLK AVDD AVSSCLPOB

 

 

 

 

 

AD9840

 

 

 

 

 

 

CLP

 

DRVDD

 

 

 

 

 

 

DRVSS

 

4 dB

 

2~36 dB

 

 

 

 

 

 

 

 

 

 

CCDIN

CDS

2:1

 

 

10-BIT

10

 

 

 

VGA

 

DOUT

 

 

 

 

 

 

MUX

 

ADC

 

 

 

 

 

 

 

 

CLP

 

 

 

 

 

 

 

 

 

10

Offset

BANDGAP

 

VRT

 

 

 

DAC

 

 

 

 

 

 

 

CLPDM

 

BUF

 

 

REFERENCE

VRB

 

 

8

 

 

 

 

 

 

INTERNAL

 

CML

 

 

CONTROL

 

 

AUX1IN

2:1

 

BIAS

 

 

REGISTERS

 

 

DVDD

 

MUX

 

 

 

 

 

AUX2IN

CLP

DIGITAL

 

INTERNAL

 

 

 

INTERFACE

 

TIMING

 

DVSS

 

 

SL SCK SDATA

SHP SHDDATA

 

 

 

SEN

 

 

CLK

 

Fig. 1-5. IC905 Block Diagram

1VDD

 

Input

SHT 20

 

Buffer

 

2

XSHT

V3B 19

3

XV3

VL 18

4

XSG3B

V3A 17

5 XSG3A

V1B 16

6

XV1

VH 15

7 XSG1B

V1A 14

 

�

V4 13

8

XSG1A

9

XV4

V2 12

10 XV2

GND 11

Fig. 1-4. IC907 Block Diagram

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