IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F) (3/3)
Pin No. | Port Name | Input/Output | Function |
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83 | DVDD | Input | D/A converting section power terminal. |
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84 | DVR | Input | Reference voltage terminal. |
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85* | LO | Output | L channel data forward rotation output terminal. |
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86 | DVSL | Input | L channel D/A converting section power terminal. |
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87* | TEST1 | Input | Test mode terminal. To be opened usually. |
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88* | TEST2 | Input | Test mode terminal. To be opened usually. |
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89* | TEST3 | Input | Test mode terminal. To be opened usually. |
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Input/Output | Microcomputer interface data input/output terminal. | ||
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94 | VDD | Input | Digital + power terminal. |
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95 | VSS | — | Digital ground terminal. |
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96 | BUCK | Input | Microcomputer interface clock input terminal. |
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97 | /CCE | Input | Microcomputer interface chip enable signal input terminal. "L": BUS0 to 3 is active. |
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98* | TEST4 | Input | Test mode terminal. To be opened usually. |
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99* | /TSMOD | Input | Local test mode selection terminal. |
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100 | /RST | Input | Reset signal input terminal. "L": Reset. |
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In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F)
30 TMAX | 29 TMAXS | 28 PDO |
LPFN 31 |
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LPFO 32 |
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PVREF 33 |
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VCOREF 34 |
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VCOF 35 |
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AVSS 36 |
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SLCO 37 |
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RFI 38 |
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AVDD 39 |
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RFCT 40 |
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RFZI 41 |
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RFRP 42 |
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FEI 43 |
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SBAD 44 |
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TSIN 45 |
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TEI 46 |
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TEZI 47 |
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FOO 48 |
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TRO 49 |
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VREF 50 |
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51 | 52 | 53 |
RFGC | TEBC | FMO |
ZDET | HSSW | P2VREF | TESIO0 | VDD | MONIT | COFS | SPDA | SPCK | SBSY | SFSY | DATA | VSS | VDD | CLCK | SBOK | IPF | MBOV | DOUT | AOUT | BCK | VSS | LRCK | EMPH | /UHSO | /HSO |
27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 |
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| TMAX |
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| Digital |
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| Status |
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| Audio output |
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| demodulation |
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| out |
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| circuit |
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| circuit |
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| VCO |
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| Synchronizing RAM | EFMdemodulation |
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| Microcomputer interface |
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| Address |
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| slicer |
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| guarantee |
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| 16KRAM |
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| Data |
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| CLV |
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| signal |
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| Correction |
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| servo |
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| circuit |
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| A/D |
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| Digital equalizer |
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| circuit |
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| adjustment circuit |
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| ROM |
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| Clock |
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| generator |
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| 1Bit |
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| LPF |
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| Servo control |
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D/A |
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| PWM |
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| DAC |
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54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 |
FVO | DMO | 2VREF | SEL | FLGA | FLGB | FLGC | FLGD | VDD | VSS | IO0 | IO1 | IO2 | IO3 | /DMOUT | /CKSE | /DACT | TESIN | TESIO1 | VSS | PXI | PXO | VDD | XVSS | XI | XO |
XVDD 801 TEST0
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
/RST
/TSMOD
TEST4
/CCE
BUCK
VSS
VDD
BUS3
BUS2
BUS1
BUS0
TEST3
TEST2
TEST1
DVSL
LO
DVR
DVDD
RO
DVSR
Figure 55 BLOCK DIAGRAM OF IC
– 55 –
