IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F) (2/3)
Pin No. | Port Name | Input/Output | Function |
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39 | AVDD | Input | Analog system power terminal. |
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40 | RFCT | Input | RFRP signal center level input terminal. |
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41 | RFZI | Input | RFRP zero cross input terminal. |
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42 | RFIP | Input | RF ripple signal input terminal. |
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43 | FEI | Input | Focus error signal input terminal. |
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44 | SBAD | Input | |
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45 | TSIN | Input | Test input terminal. To be fixed to Vref usually. |
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46 | TEI | Input | Tacking error input terminal. (Tracking servo ON: |
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47 | TEZI | Input | Tracking error, zero cross input terminal. |
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48 | FOO | Output | Focus equalizer output terminal. |
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49 | TRO | Output | Tracking equalizer output terminal. |
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50 | VREF | Input | Analog standard power terminal. |
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51 | RFGC | Output | RF amplitude adjustment control signal output terminal. |
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52 | TEBC | Output | Tracking balance control signal output terminal. |
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53 | FMO | Output | Feed equalizer output terminal. |
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54* | FVO | Output | Speed error signal or feed search EQ output terminal. |
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55 | DMO | Output | Disc equalizer output terminal. |
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56 | 2VREF | Input | Analog standard power terminal (2xVREF) |
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57 | SEL | Output | APC circuit ON/OFF signal output terminal. |
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| When laser is ON and UHS = L, |
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58* | FLGA | Output | Internal signal monitor external flag output terminal. |
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| TEZC, FOON, FOK and RFZC signals can be selected with command. |
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59* | FLGB | Output | Internal signal monitor external flag output terminal. |
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| DFCT, FOON, FMON and RFZC signals can be selected with command. |
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60* | FLGC | Output | Internal signal monitor external flag output terminal. |
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| TRON, TRSR, FOK, and SRCH signals can be selected with command. |
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61* | FLGD | Output | Internal signal monitor external flag output terminal. |
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| TRON, DMON, HYS and SHC signals can be selected with command. |
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62 | VDD | Input | Digital + power terminal. |
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63 | VSS | — | Digital ground terminal. |
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64* | IO0 | Input/Output | |
65* | IO1 |
| The input port and output port can be selected with command. In case of input port the terminal |
66* | IO2 |
| state (H/L) can be read with the read command. |
67* | IO3 |
| In case of output port the terminal state (H/L/HiZ) can be controlled with command. |
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68* | /DMOUT | Input | Terminal to set the mode to output |
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| value PWM of disc equalizer from IO2,3 terminal. "L" active |
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69* | /CKSE | Input | To be opened usually. |
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70* | /DACT | Input | DAC test mode terminal. To be opened usually. |
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71 | TESIN | Input | Test input terminal (externally provided VCO clock input terminal). To be fixed to "L" usually. |
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72 | TESIO1 | Input | Test input/output terminal. To be fixed to "L" usually. |
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73 | VSS | — | Digital ground terminal. |
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74 | PXI | Input | DSP system clock oscillation circuit input terminal. To be fixed to "L" usually. |
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75* | PXO | Output | DSP system clock oscillation circuit output terminal. |
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76 | VDD | Input | Digital + power terminal. |
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77 | XVSS | — | System clock oscillation circuit ground terminal. |
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78 | XI | Input | System clock oscillation input terminal. |
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79 | XO | Output | System clock oscillation circuit output terminal. |
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80 | XVDD | Input | System clock oscillation circuit + power terminal. |
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81 | DVSR | Input | R channel D/A converting section power terminal. |
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82* | RO | Output | R channel data forward rotation output terminal. |
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In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
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