Device Control Register | Silicon Image SSDS00-3650H-R specification

ATA REGISTERS

SSD-HXXX(I)-3650 DATA SHEET

DEVICE CONTROL REGISTER

The Device Control register is used to control the interrupt request and issue ATA software resets.

Table 27: Device Control Register

Operation	D7	D6	D5	D4	D3	D2	D1	D0
Write	-	-	-	-	1	SRST	nIEN	0

Bit(s) Description

7-4 Reserved bits.

3 Always set to 1.

2 Software Reset (SRST). When set, resets the ATA software.

1Interrupt Enable (nIEN). When set, device interrupts are disabled. There is no function in the memory-mapped mode.

0 Always set to 0.

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DOCUMENT: 3650H-02DSR

JUNE 17, 2008

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Silicon Image SSDS00-3650H-R manual Device Control Register, Operation Write, NIEN Bits Description

Contents

Overview FeaturesSisecure Host and/or software IP Revision History UpdatedDocument No Release Date Changes Table of Contents SSD-HXXXI-3650 Data Sheet Related Documentation Sales and Support Part Numbering SSD-HXXXI-3650 Data Sheet List of Figures List of Figures List of Tables ATA Command Block and Set Description Write Long Sectors 32h, 33h SSD-HXXXI-3650 Data Sheet Physical Dimensions Physical Specifications Pin Locations System Power Requirements Product SpecificationsSystem Performance System Reliability Environmental Specifications Product Capacity Specifications047,674,880 046,240 2030 098,446,336 098,528 4066 Pin Assignments Electrical SpecificationPin Signal Name Pins Type Description Signal DescriptionsData Inputs/Outputs. This is the 8-bit or Disk Active/Slave Present. This open Controller by -IORD and -IOWR. This signal DMA Request. This signal is used for DMAGround. The device ground signal Interrupt Request. This signal is an active Capacitance Absolute Maximum Ratings Symbol Parameter 5V ±10% Units Minimum Maximum DC Characteristics O Access Read Timing Access Read Timing O Access Write Timing Access Write Timing True IDE Read/Write Access Timing True IDE Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing ATA and True IDE Register Decoding Task File Register SpecificationCS0# CS1# DA02 DA01 DA00 ATA Registers Error Register Read/Write Feature Byte Feature RegisterOperation Sector Count Register Read/Write Sector Count Default Value Read/Write Sector Number RegisterLogical Block Number bits A07-A00 LBA Addressing Low Cylinder Low RegisterLogical Block Number bits A15-A08 LBA Addressing Logical Block Number bits A23-A16 LBA Addressing Cylinder High Register LBA27 LBA26 LBA25 LBA24 Drive/Head Register Status Register Drive Write Fault DWF. Always set toCorrected Data CORR. Always set to Operation Read/Write ATA Command Code Command Register Alternate Status Register Operation Write Device Control RegisterNIEN Bits Description Device Address Register Read/Write NWTG NHS3 NHS2 NHS1 NHS0 NDS1 NDS0 Default Value ATA Command Block and Set Description ATA Command Block and SET DescriptionATA Command Set Class Command Name Registers Used Code ATA Command Set Check Power Mode 98h, E5h Check Power Mode 98h, E5hRegister Executive Drive Diagnostic 90h Executive Drive Diagnostic 90h Format Track 50h Drive Head Number LBA27-24 Command 50hFormat Track 50h Identify Drive ECh Identify Drive ECh Identify Drive Drive Attribute Data Word Data Default Bytes Data Description Address Identify Drive Drive Attribute Data Idle 97h, E3h Idle 97h, E3h Idle Immediate 95h, E1h Idle Immediate 95h, E1h Initialize Drive Parameters 91h Initialize Drive Parameters 91h Recalibrate 1Xh Drive Command 1XhRecalibrate 1Xh Read Buffer E4h Read Buffer E4h Read DMA C8h Drive Head Number LBA27-24 Command C8hRead DMA C8h Read Multiple C4h Drive Head Number LBA27-24 Command C4hRead Multiple C4h Read Sector 20h, 21h Drive Head Number LBA27-24 Command 20h or 21hRead Sector 20h, 21h Read Long Sectors 22h, 23h Drive Head Number LBA27-24 Command 22h or 23hRead Long Sectors 22h, 23h Read Verify Sectors 40h, 41h Drive Head Number LBA27-24 Command 40h or 41hRead Verify Sectors 40h, 41h Seek 7Xh Drive Head Number LBA27-24 Command 7XhSeek 7Xh Set Features EFh Set Features EFhSet Features’ Attributes Feature Operation Set Multiple Mode C6h Set Multiple Mode C6h Set Sleep Mode 99h, E6h Set Sleep Mode 99h, E6h Standby 96h, E2h Standby 96h, E2h Standby Immediate 94h, E0h Standby Immediate 94h, E0h Write Buffer E8h Write Buffer E8h Write DMA CAh Drive Head NumberLBA27-24 Command CAhWrite DMA CAh Write Multiple C5h Drive Head NumberLBA27-24 Command C5hWrite Multiple C5h Write Sectors 30h, 31h Drive Head Number LBA27-24 Command 30h or 31hWrite Sectors 30h, 31h Write Long Sectors 32h, 33h Drive Head Number LBA27-24 Command 32h or 33hWrite Long Sectors 32h, 33h Erase Sectors C0h Drive Head Number LBA27-24 Command C0hErase Sectors C0h Extended Error Codes Description Extended Error CodesRequest Sense 03h Request Sense 03h Translate Sector 87h Drive Head Number LBA27-24 Command 87hTranslate Sector 87h Wear-Level F5h Wear-Level F5h Write Multiple w/o Erase CDh Drive Head Number LBA27-24 Command CDhWrite Multiple w/o Erase CDh Write Sectors w/o Erase 38h Drive Head Number LBA27-24 Command 38hWrite Sectors w/o Erase 38h Write Verify 3Ch Drive Head Number LBA27-24 Command 3ChWrite Verify 3Ch Part Numbering Sales and SupportPart Numbering Nomenclature 3650 Part Number Capacity Part Numbers Standard Back Label with Lot Related DocumentationFront Label Code Information Related Documentation Click here

Silicon Image SSDS00-3650H-R Device Control Register, Operation Write, NIEN Bits Description

Models: SSDS00-3650H-R

Table 27: Device Control Register

Operation

Write

SRST

nIEN

Bit(s) Description

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