SSD-HXXX(I)-3650 DATA SHEET

ATA REGISTERS

DEVICE ADDRESS REGISTER

The Device Address register is used to maintain compatibility with ATA disk drive interfaces.

Table 28: Device Address Register

Operation

D7

D6

D5

D4

D3

D2

D1

D0

Read/Write

-

nWTG

nHS3

nHS2

nHS1

nHS0

nDS1

nDS0

 

 

 

 

 

 

 

 

 

Default Value

0

0

1

1

1

1

1

0

 

 

 

 

 

 

 

 

 

Bit(s) Description

7 Reserved bit.

6 Write Gate (nWTG). Low when a write to the device is in process.

5-2 nHS3 to nHS0. The negated binary address of the currently selected head.

1nDS1. Low when drive 1 is selected and active.

0nDS0. Low when drive 0 is selected and active.

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JUNE 17, 2008

DOCUMENT: 3650H-02DSR

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Silicon Image SSDS00-3650H-R manual Device Address Register, Read/Write NWTG NHS3 NHS2 NHS1 NHS0 NDS1 NDS0 Default Value