Silicon Image SSDS00-3650H-R manual True IDE Read/Write Access Timing

SSD-HXXX(I)-3650 DATA SHEET ELECTRICAL SPECIFICATION

True IDE Read/Write Access Timing

			tICL
ADDRESS Valid
CS0, CS1, DA[2::0]
	tAVRWL		tAX16H
			tAXRWH
____ _____			tRWPW
DIOR,DIOW
			tDVWL
WRITE
DD[15::00]
			tDXWH
READ
DD[15::00]
			tDVRL
		tIOST	tDXRH
			tIOPW
IORDY
______
IOIS16	tAV16L

Figure 6: True IDE Read/Write Access Timing Diagram

Table 14: True IDE Read/Write Access Timing

Symbol	Parameter	Minimum	Maximum	Units
tICL	Cycle Time	100	-	ns
tAVRWL	Address Valid to DIOR,DIOW Setup Time	15	-	ns
tRWPW	DIOR, DIOW Pulse Width	65	-	ns
tDVWL	DIOW Data Setup Time	20	-	ns
tDXWH	DIOW Data Hold Time	5	-	ns
tDVRL	DIOR Data Setup Time	15	-	ns
tDXRH	DIOR Data Hold Time	5	-	ns
tAV16L	Address Valid to IOCS16 Assertion	-	(1)	ns
tAX16H	Address Valid to IOCS16 Negation	-	(1)	ns
tAXRWH	DIOW,DIOR to Address Valid Hold Time	10	-	ns
tIOST	IORDY Setup Time	-	(1)	ns
tIOPW	IORDY Pulse Width	-	(1)	ns

Note: (1) IOIS16 and INPACK are not supported.

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PAGE 12 JUNE 17, 2008 DOCUMENT: 3650H-02DSR