Silicon Laboratories SI4734/35-B20 manual Si4734/35-B20, SCLK Frequency

Si4734/35-B20

Table 7. SPI Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter						Symbol	Test Condition	Min	Typ	Max	Unit
SCLK Frequency						fCLK		0	—	2.5	MHz
SCLK High Time						tHIGH		25	—	—	ns
SCLK Low Time						tLOW		25	—	—	ns
SDIO Input,					to SCLK↑ Setup	tS		15	—	—	ns
				SEN
SDIO Input to SCLK↑ Hold						tHSDIO		10	—	—	ns
	Input to SCLK↓ Hold					tHSEN		5	—	—	ns
SEN
SCLK↓ to SDIO Output Valid						tCDV	Read	2	—	25	ns
SCLK↓ to SDIO Output High Z						tCDZ	Read	2	—	25	ns
SCLK,			SDIO, Rise/Fall time			tR, tF		—	—	10	ns
		SEN,

Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST.

SCLK

SEN

SDIO

70%

30%

70%

30%

70%

30%

tS	tS
C7	C6–C1

tHIGH tLOW tHSDIO

C0D7

tR tF

D6–D1

tHSEN

D0

Control Byte In 8 Data Bytes In

Figure 6. SPI Control Interface Write Timing Parameters

SCLK

SEN

SDIO

70%

30%

70%

30%

70%

30%

tS

tS

C7

C6–C1

tCDV

tHSDIO

C0

tHSEN

tCDZ

D7 D6–D1D0

Control Byte In	Bus	16 Data Bytes Out
	Turnaround	(SDIO or GPO1)

Figure 7. SPI Control Interface Read Timing Parameters

10 Rev. 1.0